# US 10,872,649 B2 · Memory device configured to perform asymmetric write operation according to write direction

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- Number: US 10,872,649 B2
- Document ID: US10872649B2
- Status: Granted
- Kind: B2
- Application number: 16/507,536
- Filed: 2019-07-10
- Published: 2020-03-19
- Granted: 2020-12-22
- Earliest claimed: 2018-09-14
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Kyung Min Lee; Hyunsung Jung
- Web page: https://patentgrep.com/patent/US10872649B2

## CPC

- G11C 11/1657: {Word-line or row circuits}
- G11C 11/1673: {Reading or sensing circuits or methods}
- G11C 11/1675: {Writing or programming circuits or methods}
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Disclosed are memory devices including a variable resistance memory cell and a word line control circuit. A memory device including a variable resistance memory cell including a variable resistance element, a first cell transistor, and a second cell transistor, a first end of the variable resistance element connected to a bit line, a second end of the variable resistance element, a first end of the first cell transistor, and a first end of the second cell transistor connected to the common node, a second end of the first cell transistor and a second end of the second cell transistor connected to a source line, and a word line control circuit configured to separate a sub word line connected to a gate electrode of the second cell transistor from a word line connected to a gate electrode of the first cell transistor in a first write operation and to connect the word line and the sub word line to each other in a second write operation may be provided.

## Claims

### Claim 1

A memory device comprising:
a variable resistance memory cell including a variable resistance element, a first cell transistor, and a second cell transistor, a first end of the variable resistance element connected to a bit line, a second end of the variable resistance element, a first end of the first cell transistor, and a first end of the second cell transistor connected to a common node, a second end of the first cell transistor and a second end of the second cell transistor connected to a source line; and
a word line control circuit configured to separate a sub word line connected to a gate electrode of the second cell transistor from a word line connected to a gate electrode of the first cell transistor in a first write operation and to connect the word line and the sub word line to each other in a second write operation.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the word line control circuit includes:
a first control transistor configured to be turned off in response to a first power supply voltage so that the word line and the sub word line is separated from each other, and be turned on in response to a second power supply voltage so that the word line is connected to the sub word line, and
a second control transistor configured to be turned on in response to the first power supply voltage so that the second power supply voltage is supplied to the gate electrode of the second cell transistor, and be turned off in response to the second power supply voltage so that the second power supply voltage is not supplied to the gate electrode of the second cell transistor.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein the word line control circuit further includes a level shifter configured to receive and shift the first power supply voltage or the second power supply voltage, and input a shifted voltage to both the gate electrode of the first control transistor and the gate electrode of the second control transistor.

### Claim 4 (depends on 3)

The memory device of claim 3, wherein when the shifted voltage is based on the first power supply voltage, a level of the shifted voltage is identical to a level of a word line voltage applied to the word line.

### Claim 5 (depends on 2)

The memory device of claim 2, wherein the first control transistor is a PMOS transistor, and the second control transistor is an NMOS transistor.

### Claim 6 (depends on 1)

The memory device of claim 1, further comprising:
a row decoder configured to provide a word line voltage for driving the word line; and
a write driver and sense amplifier configured to generate a bit line voltage for driving the bit line or a source line voltage for driving the source line.

### Claim 7 (depends on 6)

The memory device of claim 6, wherein the memory device is configured such that:
the bit line voltage is applied to the bit line, and a ground voltage is applied to the source line in the first write operation; and
the source line voltage is applied to the source line, and the ground voltage is applied to the bit line in the second write operation.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein the variable resistance element includes:
a free layer having a variable magnetization direction;
a pinned layer having a fixed magnetization direction; and
a barrier layer between the free layer and the pinned layer.

### Claim 9

A memory device comprising:
a variable resistance element having a first end connected to a bit line; and
a word line control circuit configured to select at least one of a first path or a second path, a second end of the variable resistance element connected to a source line that is commonly on the first path and the second path, wherein
the first path includes a first cell transistor having a gate electrode connected to a word line,
the second path includes a second cell transistor having a gate electrode connected to a sub word line,
the word line control circuit includes a first control transistor and a second control transistor,
the first control transistor is configured to be turned off in response to a first power supply voltage so that the word line is separated from the sub word line, and be turned on in response to a second power supply voltage so that the word line is connected to the sub word line, and
the second control transistor is configured to be turned on in response to the first power supply voltage so that the second power supply voltage is supplied to the gate electrode of the second cell transistor, and be turned off in response to the second power supply voltage so that the second power supply voltage is not supplied to the gate electrode of the second cell transistor.

### Claim 10 (depends on 9)

The memory device of claim 9, wherein the memory device is configured such that,
the first cell transistor is turned on to enable the first path in a first write operation, and
the first cell transistor and the second cell transistor are turned on to enable both the first path and the second path in a second write operation.

### Claim 11 (depends on 10)

The memory device of claim 10, wherein the memory device is configured such that,
a bit line voltage is applied to the bit line, and a ground voltage is applied to the source line in the first write operation, and
a source line voltage is applied to the source line, and the ground voltage is applied to the bit line in the second write operation.

### Claim 12 (depends on 9)

The memory device of claim 9, wherein the word line control circuit further includes a level shifter configured to receive and shift the first power supply voltage or the second power supply voltage, and input a shifted voltage to the gate electrode of the first control transistor and the gate electrode of the second control transistor.

### Claim 13 (depends on 12)

The memory device of claim 12, wherein when the shifted voltage is based on the first power supply voltage, a level of the shifted voltage is identical to a level of a word line voltage applied to the word line.

### Claim 14 (depends on 9)

The memory device of claim 9, wherein the variable resistance element includes:
a free layer having a variable magnetization direction;
a pinned layer having a fixed magnetization direction; and
a barrier layer between the free layer and the pinned layer.

### Claim 15

A method of writing a memory cell which includes a variable resistance element having a first end connected to a bit line and a second end connected to a source line through at least one of a first path or a second path, the method comprising:
determining whether a write operation for the memory cell is a bit line write operation or a source line write operation;
selecting at least one of the first path or the second path based on a result of the determination; and
performing the bit line write operation or the source line write operation through the selected at least of the first path and the second path,
wherein the selecting includes,
selecting the first path, by a word line control circuit configured to control the first path and the second path, in response to the result of the determination indicating that the write operation is the bit line write operation, and
selecting the first path and the second path, by the word line control circuit, in response to the result of the determination indicating that the write operation is the source line write operation.

### Claim 16 (depends on 15)

The method of claim 15, wherein when the bit line write operation is performed,
applying a bit line voltage to the bit line and a ground voltage to the source line in response to the result of the determination indicating that the write operation is the bit line write operation, and
applying a source line voltage to the source line and the ground voltage to the bit line in response to the result of the determination indicating that the write operation is the source line write operation.

### Claim 17 (depends on 15)

The method of claim 15, wherein the variable resistance element includes:
a free layer having a variable magnetization direction;
a pinned layer having a fixed magnetization direction; and
a barrier layer between the free layer and the pinned layer.