# US 10,872,648 B2 · Apparatuses and methods for reducing row address to column address delay

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- Number: US 10,872,648 B2
- Document ID: US10872648B2
- Status: Granted
- Kind: B2
- Application number: 16/740,114
- Filed: 2020-01-10
- Published: 2020-05-14
- Granted: 2020-12-22
- Earliest claimed: 2018-07-17
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Charles L. Ingalls
- Web page: https://patentgrep.com/patent/US10872648B2

## CPC

- G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
- G11C 7/065: {Differential amplifiers of latching type}
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- G11C 8/10: Decoders
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a sense amplifier configured to, during a precharge phase, couple a first gut node of the sense amplifier to a second gut node of the sense amplifier and to a precharge voltage while the first gut node and the second gut node are coupled to a first digit line and a second digit line, respectively, at a first time. The sense amplifier is further configured to, during the precharge phase, decouple the first gut node from the first digit line and decouple the second gut node from the second digit line at a second time that is after the first time. The sense amplifier is further configured to transition to an activation phase in response to an activate command at a third time after the second time to perform a sense operation.

## Claims

### Claim 1

An apparatus comprising:
a memory comprising:
a sense amplifier configured to, during a precharge phase, couple a first gut node of the sense amplifier to a second gut node of the sense amplifier and to a precharge voltage while the first gut node and the second gut node are coupled to a first digit line and a second digit line, respectively, at a first time, and decouple the first gut node from the first digit line and decouple the second gut node from the second digit line at a second time that is after the first time, wherein the sense amplifier is further configured to transition to an activation phase in response to an activate command at a third time after the second time to perform a threshold voltage compensation operation and a sense operation.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the sense amplifier is further configured to, during the precharge phase, couple the first gut node with the second digit line between the first time and the second time.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the memory further comprises a memory cell coupled to the first digit line, wherein the sense amplifier is configured to perform the sense operation to sense a state of the memory cell.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the sense amplifier is further configured to transition to the precharge phase in response to a precharge command.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the first digit line is precharged to the precharge voltage between the first and second times.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the sense amplifier comprises a first transistor configured to selectively couple the first gut node to the first digit line and a second transistor configured to selectively couple the second gut node from the second digit line.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the memory further comprises a decoder circuit configured to, at the first time, cause the sense amplifier to couple the first gut node to the second gut node and to the precharge voltage.

### Claim 8 (depends on 5)

The apparatus of claim 5, wherein the decoder circuit is further configured to, at the second time, cause the sense amplifier to decouple the first gut node from the first digit line and decouple the second gut node to the second digit line.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein a wordline to an active state during the sense operation and is set to an inactive state during the precharge phase.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the sense amplifier is further configured to transition to a subsequent precharge phase after the sense operation in response to a precharge command.

### Claim 11

An apparatus including:
a sense amplifier comprising a first gut node and a second gut node, wherein the sense amplifier is coupled to a first digit line and a second digit line; and
a decoder circuit configured to transition from an activation phase to the precharge phase in response to a precharge command, wherein during the precharge phase, the decoder circuit is configured to set an isolation signal to cause the sense amplifier to decouple the first gut node from the first digit line and decouple the second gut node from the second digit line after the first gut node and the second gut node are precharged to the precharge voltage, wherein the decoder circuit is further configured to transition from the precharge phase to a subsequent activation phase in response to receipt of an activate command to cause the sense amplifier to perform a threshold voltage compensation operation based on a threshold voltage difference between at least two circuit components of the sense amplifier.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein the sense amplifier is further configured to transition to a subsequent precharge phase after the threshold voltage compensation operation in response to a second precharge command.

### Claim 13 (depends on 11)

The apparatus of claim 11, wherein the sense amplifier includes a first transistor configured to selectively couple the first gut node to the first digit line and a second transistor configured to selectively couple the second gut node to the second digit line.

### Claim 14 (depends on 11)

The apparatus of claim 11, wherein the decoder circuit is further configured to control the first and second transistors to selectively couple the first gut node to the first digit line and the second gut node to the second digit line, respectively, during the activation phase.

### Claim 15 (depends on 11)

The apparatus of claim 11, wherein the decoder circuit is further configured to deactivate a wordline during the precharge phase and to activate the wordline during at least part of the activation phase.

### Claim 16

A method, comprising:
transitioning to a precharge phase in response to receipt of a precharge command at a memory;
during the precharge phase:
precharging first and second gut nodes of a sense amplifier of the memory to a precharge voltage starting at a first time; and
decoupling the first gut node from a first digit line and decoupling the second gut node from a second digit line starting at a second time after the first time;
transitioning from the precharge phase to an activation phase in response to receipt of an activate command after the second time to perform a threshold voltage compensation operation based on a threshold voltage difference between at least two circuit components of the sense amplifier.

### Claim 17 (depends on 16)

The method of claim 16, further comprising selecting a delay between the first and second times based on time to precharge the first and second gut nodes to the precharge voltage.

### Claim 18 (depends on 16)

The method of claim 16, wherein the precharge voltage is less than an array voltage.

### Claim 19 (depends on 16)

The method of claim 16, further comprising, during the precharge phase, cross-coupling the first gut node with the second digit line and the second gut node with the first digit line.

### Claim 20 (depends on 16)

The method of claim 16, further comprising activating a wordline during or after the threshold voltage compensation operation to facilitate a sense operation associated with a memory cell coupled to the wordline and to one of the first or second digit lines.