# US 10,872,643 B2 · Systems and methods for a centralized command address input buffer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,643 B2 - Document ID: US10872643B2 - Status: Granted - Kind: B2 - Application number: 16/518,650 - Filed: 2019-07-22 - Published: 2019-12-05 - Granted: 2020-12-22 - Earliest claimed: 2018-06-04 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Yutaka Uemura; Yasuhiro Takai - Web page: https://patentgrep.com/patent/US10872643B2 ## CPC - G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories} - G11C 8/06: Address interface arrangements, e.g. address buffers - G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load} - G11C 7/1087: {Data input latches} - G11C 7/109: {Control signal input circuits} - G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management - G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - G11C 11/4082: {Address Buffers; level conversion circuits} - G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers - G11C 2207/105: Aspects related to pads, pins or terminals - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract An apparatus may include a first pad and a first input circuit coupled to the first pad. The first input circuitry may include a first signal propagation path that couples to the first pad, a latch circuit, a second signal propagation path that couples to the latch circuit, and a gate circuitry coupling between the first and second signal propagation paths. The first signal propagation path may have first signal propagation time and the second signal propagation path may have second signal propagation time that is greater than the first propagation time. ## Claims ### Claim 1 An apparatus comprising: a first pad; and a first input circuit coupled to the first pad via an input buffer, wherein the first input circuit comprises: a first signal propagation path coupled to the first pad; a latch circuit; a second signal propagation path coupled to the latch circuit; and a gate circuit between the first and second signal propagation paths, wherein the first signal propagation path is configured to have first signal propagation time and the second signal propagation path is configured to have second signal propagation time that is greater than the first signal propagation time. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the first signal propagation path comprises a first delay circuit having a first delay time, and wherein the second signal propagation path comprises a second delay circuit having a second delay time that is greater than the first delay time. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the first pad is configured to receive at least one of command and address signals, and wherein a second pad is configured to receive a chip select signal. ### Claim 4 (depends on 2) The apparatus of claim 2, wherein the first delay circuit comprises a first number of delay elements and the second delay circuit comprises a second number of delay elements that is greater than the first number of delay elements. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the gate circuit is configured to cause a signal to be transferred from the first signal propagation path to the second signal propagation path in response to a first level of a control signal, wherein the control signal is generated at least partially via an output from a pulse extender configured to lengthen a duration of time that an input received at a second pad is at the first level, and wherein the apparatus comprises: the second pad; and a second input circuit coupled to the second pad and configured to provide the control signal. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the first signal propagation path comprises a first input buffer having a first driving capability, and wherein a second input circuit comprises a second input buffer having a second driving capability that is greater than the first driving capability. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the first pad is configured to receive at least one of command and address signals, and wherein a second pad is configured to receive a chip select signal that becomes valid to the at least one of command and address signals becoming valid. ### Claim 8 A memory device comprising: a first pad; and a first input circuit coupled to the first pad, wherein the first input circuit comprises: a first delay block coupled to the first pad; a second delay block coupled to output circuitry of the first input circuit; and a gate circuit coupled between the first and second delay blocks, wherein the first delay block is configured to contribute to a first signal propagation time and the second delay block is configured to contribute to a second signal propagation time, and wherein the second delay block consumes power in response to a second pad receiving a chip select signal. ### Claim 9 (depends on 8) The memory device of claim 8, wherein the first signal propagation time and the second signal propagation time are different from each other. ### Claim 10 (depends on 9) The memory device of claim 9, wherein the second signal propagation time is greater than the first signal propagation time. ### Claim 11 (depends on 8) The memory device of claim 8, wherein the output circuitry comprises a latch configured to store at least one command and address signals in response to a latch control signal. ### Claim 12 (depends on 11) The memory device of claim 11, wherein the latch is disposed adjacent to one or more additional latches in a centralized location on the memory device. ### Claim 13 (depends on 8) The memory device of claim 8, wherein the first delay block comprises first inverting circuitry configured to cause a first delay time, wherein the second delay block comprises second inverting circuitry configured to cause a second delay time that is greater than the first delay time, and wherein the first signal propagation time is based at least in part on the first delay time and the second signal propagation time is based at least in part on the second delay time. ### Claim 14 (depends on 8) The memory device of claim 8, comprising: a second pad; and a second input circuit coupled to the second pad and configured to provide a control signal to cause the gate circuit to transmit a signal in response to a first level of the control signal, wherein a duration of time that the first level of the control signal is transmitted to the gate circuit equals a duration of time suitable for storing data received via the first pad. ### Claim 15 (depends on 14) The memory device of claim 14, wherein the first pad is configured to receive at least one of command and address signals, and wherein the chip select signal becomes valid simultaneous to the at least one of command and address signals becoming valid. ### Claim 16 (depends on 14) The memory device of claim 14, comprising: a first input buffer coupled to the first pad, wherein the first input buffer is configured to have a first driving capability; and a second input buffer coupled to the second pad, wherein the second input buffer is configured to have a second driving capability that is greater than the first driving capability. ### Claim 17 A memory device, comprising: one or more pads; and one or more input circuits respectively coupled to respective pads of the one or more pads, wherein each of the input circuits comprises: a first group of inverting logic gates coupled to a respective pad of the one or more pads; a latch circuit; a second group of inverting logic gates coupled to the latch circuit; and a gate circuit coupled to an output from the first group of inverting logic gates, wherein an output from the gate circuit is coupled to an input of the second group of inverting logic gates, wherein the first group of inverting logic gates are configured to less signal delay than the second group of inverting logic gates. ### Claim 18 (depends on 17) The memory device of claim 17, wherein the first group of inverting logic gates are configured to cause less signal delay than the second group of inverting logic gates based at least on a quantity of logic gates. ### Claim 19 (depends on 17) The memory device of claim 17, wherein each of the input circuits are configured to cause an equal delay. ### Claim 20 (depends on 17) The memory device of claim 17, wherein each of the input circuits respectively comprise an input buffer, and wherein the input buffer and the latch circuit are configured to be physically disposed in a centralized location. ### Claim 21 (depends on 17) The memory device of claim 17, wherein the gate circuit is coupled to a second pad of the one or more pads, wherein the second pad is configured to receive a chip select signal, wherein the chip select signal is enabled for a first duration of time when transmitted to the second pad, and wherein the chip select signal is extended via a pulse extender to cause the control signal to be transmitted to the gate circuit for a second duration of time greater than the first duration of time.