# US 10,872,642 B2 · System comprising a memory capable of implementing calculation operations

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- Number: US 10,872,642 B2
- Document ID: US10872642B2
- Status: Granted
- Kind: B2
- Application number: 16/224,700
- Filed: 2018-12-18
- Published: 2019-06-20
- Granted: 2020-12-22
- Earliest claimed: 2017-12-19
- Assignees: Commissariat A L'energie Atomique Et Aux Energies Alternatives
- Applicants: Commissariat à I'Énergie Atomique et aux Énergies Alternatives
- Inventors: Henri-Pierre Charles; Maha Kooli; Jean-Philippe Noel
- Web page: https://patentgrep.com/patent/US10872642B2

## CPC

- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G06F 3/061: {Improving I/O performance}
- G06F 3/0638: {Organizing or formatting or addressing of data}
- G06F 3/0673: {Single storage device}
- G11C 8/06: Address interface arrangements, e.g. address buffers
- G11C 7/109: {Control signal input circuits}
- H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A memory circuit including: a plurality of elementary storage cells arranged in an array of rows and of columns; a data input/output port; an address input port; a mode selection input port; and an internal control circuit configured to: read a mode selection signal applied to the mode selection port; when the mode selection signal is in a first state, read an address of a row from the address input port and implement a read or write operation in this row; and when the mode selection signal is in a second state, read from the data input/output port an instruction signal and implement an operation including the simultaneous activation in read or write mode of at least two rows.

## Claims

### Claim 1

A memory circuit comprising:
a plurality of elementary storage cells arranged in an array of rows and of columns;
a data input/output port;
an address input port different from the data input/output;
a mode selection input port; and
an internal control circuit configured to:
read a mode selection signal applied to the mode selection port;
when the mode selection signal is in a first state, read an address of a row from the address input port and implement, via the data input/output port, a read or write operation in this row; and
when the mode selection signal is in a second state, read from the data input/output port an instruction signal and implement an operation comprising the simultaneous activation in read or write mode of at least two rows selected according to the instruction signal,
wherein the instruction signal comprises a first field defining a type of operation to be implemented by the internal control circuit, wherein the internal control circuit is capable of, when the mode selection signal is in the second state, implementing a calculation operation comprising the simultaneous activation in read mode of at least two rows selected according to the instruction signal, and wherein the internal control circuit is further configured to, when the mode selection signal is in the second state, read an address signal from the address input port and write at the corresponding address of the memory circuit a result of the calculation operation.

### Claim 2 (depends on 1)

The memory circuit of claim 1, wherein the internal control circuit is capable of, when the mode selection signal is in the second state, implementing an operation of writing same data into at least two rows selected according to the instruction signal.

### Claim 3 (depends on 1)

The memory circuit of claim 1, wherein the instruction signal comprises a second field defining the addresses of the rows to be selected for the implementation of the operation.

### Claim 4 (depends on 3)

The memory circuit of claim 3, further comprising a row selection circuit configured to generate, from the second field of the instruction signal, a row selection vector over N bits, where N is an integer designating the number of rows of the array.

### Claim 5 (depends on 4)

The memory circuit of claim 4, wherein the second field comprises a first sub-field and a second sub-field of log2(N) bits each, where N is an integer designating the number of rows of the array.

### Claim 6 (depends on 5)

The memory circuit of claim 5, wherein the row selection circuit is capable of generating the row selection vector from the first and second sub-fields of the second field of the instruction signal.

### Claim 7 (depends on 6)

The memory circuit of claim 6, wherein the row selection circuit comprises Q=log2(N) stages Ej, j being an integer in the range from 0 to Q−1, each stage Ej comprising a first logic selection cell comprising first and second input nodes and first and second output nodes, and 2j second logic selection cells, each comprising first, second, and third input nodes and first and second output nodes.

### Claim 8 (depends on 7)

The memory circuit of claim 7, wherein:
in each stage Ej, each second cell of the stage has its second and third input nodes respectively connected to the first and second output nodes of the first cell in the stage; and
in each stage Ej except for stage EQ−1, each second cell of the stage has its first output node connected to the first input node of one of the second cells of stage Ej+1 and its second output node connected to the first input node of another one of the second cells of stage Ej+1.

### Claim 9 (depends on 7)

The memory circuit of claim 7, wherein:
each first cell comprises first and second logic OR gates, the first OR gate having a first input connected to the first input node of the cell, a second input connected to the second input node of the cell, and an output connected to the first output node of the cell, and the second OR gate having a first input connected to the first input node of the cell, a second input coupled to the second input node of the cell via an inverter, and an output connected to the second output node of the cell; and
each second cell comprises first and second logic AND gates, the first AND gate having a first input connected to the first input node of the cell, a second input connected to the second input node of the cell, and an output connected to the first output node of the cell, and the second AND gate having a first input connected to the first input node of the cell, a second input connected to the third input node of the cell, and an output connected to the second output node of the cell.

### Claim 10 (depends on 7)

The memory circuit of claim 7, wherein the internal control circuit is configured to, when the mode selection signal is in the second state, apply the log2(N) bits of the first sub-field respectively to the log2(N) second input nodes of the first cells (701) of the row selection circuit, and apply the log 2(N) bits of the second sub-field respectively to the log2(N) first input nodes of the first cells of the row selection circuit.

### Claim 11 (depends on 1)

A system comprising a microprocessor and the memory circuit of claim 1, the system further comprising:
a data bus coupling a data input/output port of the microprocessor to the data input/output port of the memory circuit;
an address bus coupling an address output port of the microprocessor to the address input port of the memory circuit; and
a mode selection bus coupling a mode selection output port of the microprocessor to the mode selection input port of the memory circuit.

### Claim 12 (depends on 11)

The system of claim 11, wherein the microprocessor is configured to:
in a first operating mode:
apply a mode selection signal in the first state to the mode selection bus;
apply a row address signal to the address bus; and
read or write data into the corresponding row of the memory circuit via the data bus, and
in a second operating mode:
apply a mode selection signal in the second state to the mode selection bus; and
apply an instruction signal to the data bus.

### Claim 13

A memory circuit comprising:
a plurality of elementary storage cells arranged in an array of rows and of columns;
a data input/output port;
an address input port different from the data input/output;
a mode selection input port;
an internal control circuit configured to:
read a mode selection signal applied to the mode selection port;
when the mode selection signal is in a first state, read an address of a row from the address input port and implement, via the data input/output port, a read or write operation in this row; and
when the mode selection signal is in a second state, read from the data input/output port an instruction signal and implement an operation comprising the simultaneous activation in read or write mode of at least two rows selected according to the instruction signal,
wherein the instruction signal comprises a first field defining a type of operation to be implemented by the internal control circuit and a second field defining the addresses of the rows to be selected for the implementation of the operation; and
a row selection circuit configured to generate, from the second field of the instruction signal, a row selection vector over N bits, where N is an integer designating the number of rows of the array.

### Claim 14 (depends on 13)

The memory circuit of claim 13, wherein the internal control circuit is capable of, when the mode selection signal is in the second state, implementing an operation of writing same data into at least two rows selected according to the instruction signal.

### Claim 15 (depends on 13)

The memory circuit of claim 13, wherein the second field comprises a first sub-field and a second sub-field of log2(N) bits each, where N is an integer designating the number of rows of the array.

### Claim 16 (depends on 15)

The memory circuit of claim 15, wherein the row selection circuit is capable of generating the row selection vector from the first and second sub-fields of the second field of the instruction signal.

### Claim 17 (depends on 16)

The memory circuit of claim 16, wherein the row selection circuit comprises Q=log2(N) stages Ej, j being an integer in the range from 0 to Q−1, each stage Ej comprising a first logic selection cell comprising first and second input nodes and first and second output nodes, and 2j second logic selection cells, each comprising first, second, and third input nodes and first and second output nodes.

### Claim 18 (depends on 17)

The memory circuit of claim 17, wherein:
in each stage Ej, each second cell of the stage has its second and third input nodes respectively connected to the first and second output nodes of the first cell in the stage; and
in each stage Ej except for stage EQ−1, each second cell of the stage has its first output node connected to the first input node of one of the second cells of stage Ej+1 and its second output node connected to the first input node of another one of the second cells of stage Ej+1.

### Claim 19 (depends on 17)

The memory circuit of claim 17, wherein:
each first cell comprises first and second logic OR gates, the first OR gate having a first input connected to the first input node of the cell, a second input connected to the second input node of the cell, and an output connected to the first output node of the cell, and the second OR gate having a first input connected to the first input node of the cell, a second input coupled to the second input node of the cell via an inverter, and an output connected to the second output node of the cell; and
each second cell comprises first and second logic AND gates, the first AND gate having a first input connected to the first input node of the cell, a second input connected to the second input node of the cell, and an output connected to the first output node of the cell, and the second AND gate having a first input connected to the first input node of the cell, a second input connected to the third input node of the cell, and an output connected to the second output node of the cell.

### Claim 20 (depends on 17)

The memory circuit of claim 17, wherein the internal control circuit is configured to, when the mode selection signal is in the second state, apply the log2(N) bits of the first sub-field respectively to the log2(N) second input nodes of the first cells (701) of the row selection circuit, and apply the log 2(N) bits of the second sub-field respectively to the log2(N) first input nodes of the first cells of the row selection circuit.

### Claim 21 (depends on 13)

A system comprising a microprocessor and the memory circuit of claim 13, the system further comprising:
a data bus coupling a data input/output port of the microprocessor to the data input/output port of the memory circuit;
an address bus coupling an address output port of the microprocessor to the address input port of the memory circuit; and
a mode selection bus coupling a mode selection output port of the microprocessor to the mode selection input port of the memory circuit.

### Claim 22 (depends on 21)

The system of claim 21, wherein the microprocessor is configured to:
in a first operating mode:
apply a mode selection signal in the first state to the mode selection bus;
apply a row address signal to the address bus; and
read or write data into the corresponding row of the memory circuit via the data bus, and
in a second operating mode:
apply a mode selection signal in the second state to the mode selection bus; and
apply an instruction signal to the data bus.

### Claim 23 (depends on 13)

The memory circuit of claim 13, wherein the internal control circuit is capable of, when the mode selection signal is in the second state, implementing a calculation operation comprising the simultaneous activation in read mode of at least two rows selected according to the instruction signal.

### Claim 24 (depends on 23)

The memory circuit of claim 23, wherein the internal control circuit is further configured to, when the mode selection signal is in the second state, read an address signal from the address input port and write at the corresponding address of the memory circuit a result of the calculation operation.