# US 10,872,641 B2 · Nwell and subtrate taps in memory layout

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- Number: US 10,872,641 B2
- Document ID: US10872641B2
- Status: Granted
- Kind: B2
- Application number: 16/454,692
- Filed: 2019-06-27
- Published: 2020-10-22
- Granted: 2020-12-22
- Earliest claimed: 2019-04-22
- Assignees: Advanced Micro Devices, Inc.
- Applicants: Advanced Micro Devices, Inc.
- Inventors: Russell Schreiber; Keith A. Kasprak
- Web page: https://patentgrep.com/patent/US10872641B2

## CPC

- G11C 7/06: Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits}
- H10D 89/10: Integrated device layouts
- G11C 11/412: using field-effect transistors only
- G11C 11/419: Read-write [R-W] circuits
- H10B 10/12: {comprising a MOSFET load element}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 11/417: for memory cells of the field-effect type
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A circuit includes a repeating series of first circuits and a repeating series of second circuits placed next to the repeating series of first circuits and interacts with corresponding portions of the first circuits in the series. The repeating series of second circuits is formed in diffusion regions and diffusion wells which extend along the direction in which the second circuits repeat. The repeating series of the first and second circuits is interrupted by at least one dummy circuit region, which occupies the space of one or more instances of the first and second repeating series. The dummy circuit region also includes taps for biasing the diffusion regions and diffusion wells of the second circuits.

## Claims

### Claim 1

An integrated circuit chip comprising:
a repeating series of first circuits extending along a first direction in which the first circuits are repeated;
a repeating series of second circuits placed next to the repeating series of first circuits and formed along diffusion regions and wells which extend in the first direction, the second circuits interacting with corresponding portions of the first circuits; and
a dummy circuit region interrupting the repeating series of second circuits and the repeating series of first circuits at an interior location along each series with pluralities of the first and second circuits before and after the interior location along each respective series, the dummy circuit region not including a functioning instance of the first or second circuits, and including taps tying the diffusion regions and wells to power supply voltages.

### Claim 2 (depends on 1)

The integrated circuit chip of claim 1, wherein the repeating series of first circuits comprises memory bitcells, and the repeating series of second circuits comprises senseamp and write driver circuits.

### Claim 3 (depends on 2)

The integrated circuit chip of claim 2, further comprising a repeating series of memory bitcells disposed in a third region at an opposite side of the repeating series of second circuits from the repeating series of first circuits, and wherein the dummy circuit region spans the third region.

### Claim 4 (depends on 1)

The integrated circuit chip of claim 1, wherein the dummy circuit region includes a non-functioning instance of the first circuits.

### Claim 5 (depends on 4)

The integrated circuit chip of claim 4, wherein the dummy circuit region includes two or more non-functioning instances of the first circuits.

### Claim 6 (depends on 4)

The integrated circuit chip of claim 4, wherein the non-functioning instance of the first circuits has positive and negative power supply conductors coupled to a more negative power supply rail.

### Claim 7 (depends on 1)

The integrated circuit chip of claim 1, wherein the dummy circuit region includes multiple taps in each of the diffusion regions and wells.

### Claim 8

A circuit comprising:
a repeating series of first circuits extending along a first direction in which the first circuits are repeated;
a repeating series of second circuits placed next to the repeating series of first circuits and formed along diffusion regions and wells which extend in the first direction, the second circuits interacting with corresponding portions of the first circuits; and
a dummy circuit region interrupting the repeating series of second circuits and the repeating series of first circuits at an interior location along each series with pluralities of the first and second circuits before and after the interior location along each respective series, the dummy circuit region not including a functioning instance of the first or second circuits, and including taps tying the diffusion regions and wells to power supply voltages.

### Claim 9 (depends on 8)

The circuit of claim 8, wherein the repeating series of first circuits comprises memory bitcells, and the repeating series of second circuits comprises senseamp and write driver circuitry.

### Claim 10 (depends on 9)

The circuit of claim 9, further comprising a repeating series of memory bitcells disposed in a third region at an opposite side of the repeating series of second circuits from the repeating series of first circuits, and wherein the dummy circuit region spans the third region.

### Claim 11 (depends on 8)

The circuit of claim 8, wherein the dummy circuit region includes a non-functioning instance of the first circuits.

### Claim 12 (depends on 11)

The circuit of claim 11, wherein the dummy circuit region includes two or more non-functioning instances of the first circuits.

### Claim 13 (depends on 11)

The circuit of claim 11, wherein the non-functioning instance of the first circuits has positive and negative power supply conductors tied off to a more negative power supply rail.

### Claim 14 (depends on 8)

The circuit of claim 8, wherein the dummy circuit region includes multiple taps in each of the diffusion regions and wells.

### Claim 15

A method comprising:
operating a repeating series of first circuits extending along a first direction in which the first circuits are repeated;
operating a repeating series of second circuits placed next to the repeating series of first circuits, the second circuits interacting with corresponding portions of the first circuits; and
at a dummy circuit region which interrupts the repeating series of first circuits and the repeating series of second circuits at an interior location along each series with pluralities of the first and second circuits before and after the interior location along each respective series, biasing diffusion regions and wells which extend in the first direction, the diffusion regions biased to power supply voltages.

### Claim 16 (depends on 15)

The method of claim 15, wherein the repeating series of first circuits comprises memory bitcells, and the repeating series of second circuits comprises senseamp and write driver circuitry.

### Claim 17 (depends on 16)

The method of claim 16, wherein the dummy circuit region spans a third region comprising a repeating series of memory bitcells disposed at an opposite side of the repeating series of second circuits from the repeating series of first circuits.

### Claim 18 (depends on 15)

The method of claim 15, wherein the dummy circuit region includes a non-functioning instance of the first circuits.

### Claim 19 (depends on 18)

The method of claim 18, wherein the dummy circuit region includes two or more non-functioning instances of the first circuits.

### Claim 20 (depends on 15)

The method of claim 15, wherein biasing diffusion regions and wells includes biasing with multiple taps in each of the diffusion regions and wells.