# US 10,872,640 B2 · Capacitive voltage dividers coupled to voltage regulators

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- Number: US 10,872,640 B2
- Document ID: US10872640B2
- Status: Granted
- Kind: B2
- Application number: 16/119,564
- Filed: 2018-08-31
- Published: 2020-03-05
- Granted: 2020-12-22
- Earliest claimed: 2018-08-31
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Matthew D. Rowley
- Web page: https://patentgrep.com/patent/US10872640B2

## CPC

- G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)}
- G06F 1/26: Power supply means, e.g. regulation thereof (for memories G11C)
- G06F 1/28: Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
- G06F 1/30: Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24)
- G06F 1/3275: {Power saving in memory, e.g. RAM, cache}
- G06F 1/3296: by lowering the supply or operating voltage
- G11C 5/148: {Details of power up or power down circuits, standby circuits or recovery circuits}
- H02M 1/0045: {Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- Y02D 30/50: in wire-line communication networks, e.g. low power modes or reduced link rate
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A method of operating a memory sub-system includes receiving an input voltage at a power management (PM) component of a memory sub-system, where the PM component includes a capacitive voltage divider (CVD), a linear voltage regulator (LVR), and a switching voltage regulator (SVR). The method includes determining whether the input voltage corresponds to a low power mode of the memory sub-system and that the input voltage is higher than an uppermost supply voltage at which a memory component of the memory sub-system is configured to operate. The method further includes selectably coupling, responsive to a determination of the low power mode, the CVD and the LVR and sequentially reducing the input voltage by the CVD and the LVR to a supply voltage for the memory component, where the supply voltage is not higher than the uppermost supply voltage at which the memory component is configured to operate.

## Claims

### Claim 1

A method, comprising:
receiving an input voltage at a power management (PM) component of a memory sub-system, wherein the PM component comprises a capacitive voltage divider (CVD), a linear voltage regulator (LVR), and a switching voltage regulator (SVR);
determining, by a monitoring unit of the PM component, that the input voltage corresponds to a low power mode of the memory sub-system and that the input voltage is higher than an uppermost supply voltage at which a memory component of the memory sub-system is configured to operate;
selectably coupling, responsive to determination of the low power mode, the CVD and the LVR; and
sequentially reducing the input voltage by the CVD and the LVR to a supply voltage for the memory component, wherein the supply voltage is not higher than the uppermost supply voltage at which the memory component is configured to operate.

### Claim 2 (depends on 1)

The memory sub-system of claim 1, wherein the memory sub-system is a solid-state drive (SSD).

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
receiving the input voltage as a first supply voltage to the CVD;
responsive to the determination of the low power mode, disabling the SVR and enabling the LVR;
modifying the first supply voltage, by the CVD, to a second supply voltage compatible with operation of the LVR, wherein the second supply voltage is less than a supply voltage compatible with operation of the SVR;
providing the second supply voltage to the LVR;
reducing the second supply voltage, by the LVR, to a third supply voltage compatible with operation of the memory component; and
providing, by the PM component, the third supply voltage to the memory component.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
responsive to the determination of the low power mode, disabling the SVR and enabling the LVR;
receiving the input voltage as a first supply voltage to the LVR;
reducing the first supply voltage, by the LVR, to a second supply voltage compatible with operation of the CVD;
providing the second supply voltage to the CVD;
reducing the second supply voltage, by the CVD, to a third supply voltage compatible with operation of the memory component; and
providing, by the PM component, the third supply voltage to the memory component.

### Claim 5 (depends on 1)

The method of claim 1, further comprising reducing, by the LVR, the first supply voltage to a particular second supply voltage that is divisible by the CVD to the third supply voltage compatible with operation of a particular memory component.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
configuring the LVR to produce a first input-output voltage differential that is less than a second input-output voltage differential that the SVR is configured to produce;
wherein a two-stage reduction of the input voltage by the LVR and the CVD is more energy efficient than a one- or two-stage reduction of the input voltage utilizing the SVR based, at least in part, on a difference between the first and second input-output voltage differentials.

### Claim 7

A memory sub-system, comprising:
a capacitive voltage divider (CVD) selectably coupled to one of a linear voltage regulator (LVR) and a switching voltage regulator (SVR); and
a controller coupled to the CVD, the LVR, and the SVR, wherein the controller is configured, responsive to a determination that the memory sub-system receives an input voltage in a particular range as a first supply voltage, to direct that:
the CVD reduces, by connection of a plurality of capacitors, the first supply voltage to a second supply voltage compatible with operation of the LVR; and
the CVD is coupled to the LVR, instead of the SVR, to supply the second supply voltage.

### Claim 8 (depends on 7)

The memory sub-system of claim 7, wherein the memory sub-system is a solid-state drive (SSD).

### Claim 9 (depends on 7)

The memory sub-system of claim 7, further comprising a monitoring unit configured to determine whether the memory sub-system is in a low power mode or a normal power mode.

### Claim 10 (depends on 7)

The memory sub-system of claim 7, wherein the controller is further configured, responsive to a determination that the memory sub-system is in a low power mode, rather than a normal power mode, to decouple the CVD from the SVR and couple the CVD to the LVR.

### Claim 11 (depends on 7)

The memory sub-system of claim 7, wherein the controller is further configured, responsive to a determination that the memory sub-system is in a normal power mode, rather than a low power mode, to decouple the CVD from the LVR and couple the CVD to the SVR.

### Claim 12 (depends on 7)

The memory sub-system of claim 7, wherein the LVR is configured to reduce the second supply voltage to a third supply voltage compatible with operation of a memory component of the memory sub-system.

### Claim 13 (depends on 7)

The memory sub-system of claim 7, wherein the LVR is a low dropout (LDO) regulator.

### Claim 14 (depends on 7)

The memory sub-system of claim 7, wherein the SVR is selected from a buck regulator and a buck/boost regulator.

### Claim 15

A memory sub-system, comprising:
a primary power supply (PPS) selectably coupled to one of a linear voltage regulator (LVR) and a switching voltage regulator (SVR); and
a controller coupled to the LVR and the SVR, wherein the controller is configured, responsive to a determination that the memory sub-system receives an input voltage in a particular range from the PPS as a first supply voltage, to direct that:
the LVR reduces the input voltage to a second supply voltage compatible with operation of a capacitive voltage divider (CVD); and
the LVR is coupled to the CVD, instead of the SVR, to supply the second supply voltage.

### Claim 16 (depends on 15)

The memory sub-system of claim 15, wherein the second supply voltage compatible with operation of the CVD is a particular voltage that is divisible by the CVD to produce a third supply voltage compatible with operation of a particular memory component of the memory sub-system.

### Claim 17 (depends on 15)

The memory sub-system of claim 15, wherein the controller is further configured, responsive to a determination that the memory sub-system is in a low power mode, rather than a normal power mode, to decouple the SVR from the PPS and couple the LVR to the PPS to receive the input voltage.

### Claim 18 (depends on 15)

The memory sub-system of claim 15, wherein the controller is further configured, responsive to a determination that the memory sub-system is in a normal power mode, rather than a low power mode, to decouple the LVR from the PPS and couple the SVR to the PPS to receive the input voltage.

### Claim 19 (depends on 15)

The memory sub-system of claim 15, wherein:
the LVR is a low dropout (LDO) regulator configured to reduce the first supply voltage to a second supply voltage compatible with operation of the CVD; and
the CVD is configured to reduce the second supply voltage to a third supply voltage compatible with operation of a memory component of the memory sub-system.

### Claim 20 (depends on 15)

The memory sub-system of claim 15, wherein the input voltage in the particular range corresponds to the memory sub-system being in either a standby mode, a slumber mode, or a sleep mode in which a lower input voltage is supplied relative to a mode that operates at a higher input voltage.

### Claim 21 (depends on 15)

The memory sub-system of claim 15, wherein the higher input voltage is 12 volts (V) or higher and the lower input voltage is in a range of from 2V-5V.