# US 10,872,578 B2 · Shift register unit, gate driving circuit and driving method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,578 B2 - Document ID: US10872578B2 - Status: Granted - Kind: B2 - Application number: 15/766,659 - Filed: 2017-09-30 - Published: 2019-02-28 - Granted: 2020-12-22 - Earliest claimed: 2017-04-12 - Assignees: Boe Technology Group Co., Ltd.; Hefei Xinsheng Optoelectronics Technology Co., Ltd. - Applicants: BOE Technology Group Co., Ltd.; Hefei Xinsheng Optoelectronics Technology Co., Ltd. - Inventors: Jian Zhao; Hui Wang - Web page: https://patentgrep.com/patent/US10872578B2 ## CPC - G09G 3/3677: {suitable for active matrices only} - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G11C 19/287: {Organisation of a multiplicity of shift registers} - G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2320/0209: Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display - G09G 2320/0252: Improving the response speed - H04N 13/359: Switching between monoscopic and stereoscopic modes - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G11C: STATIC STORES (semiconductor memory devices H10B) - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract A shift register unit and a driving method thereof, a gate driving circuit, and an array substrate are provided, and the shift register unit includes: an input sub-circuit connected between a signal input terminal and a pull-up node, an output sub-circuit connected between the pull-up node and a signal output terminal; a reset sub-circuit connected between a reset terminal, the pull-up node and the signal output terminal; and a clock signal selection sub-circuit having input terminals connected to a first clock signal terminal and a second clock signal terminal, and a first output terminal connected to the output sub-circuit, and for selecting to provide either a first clock signal or a second clock signal to the output sub-circuit according to voltage levels at the first control terminal and the second control terminal. ## Claims ### Claim 1 A gate driving circuit, comprising N stages of a shift register unit, wherein the shift register unit comprises: an input sub-circuit connected between a signal input terminal and a pull-up node, and configured to input a signal to the pull-up node, an output sub-circuit connected between the pull-up node and a signal output terminal, and configured to output a pulse signal to the signal output terminal under control of the pull-up node; a reset sub-circuit connected between a reset terminal, the pull-up node, and the signal output terminal, and configured to reset the pull-up node and the signal output terminal under control of the reset terminal; and a clock signal selection sub-circuit having input terminals connected to a first clock signal terminal and a second clock signal terminal, control terminals connected to a first control terminal and a second control terminal, and a first output terminal connected to the output sub-circuit, and configured to select to provide either a first clock signal or a second clock signal to the output sub-circuit according to voltage levels at the first control terminal and the second control terminal, as an input clock signal to the output sub-circuit, wherein the input clock signal is the same as one of the first clock signal and the second clock signal in a case where the voltage levels at the first control terminal and the second control terminal are opposite, wherein a shift register unit in a k-th stage is configured to scan a corresponding gate line, and a signal output terminal of the shift register unit in the k-th stage is connected to a signal input terminal of the shift register unit in an (k+1)-th stage via a first switching transistor corresponding to the k-th stage and further connected to a signal input terminal of the shift register unit in a (k+2)-th stage via a second switching transistor corresponding to the k-th stage, where k≥3, N and k are integers, and a signal input terminal of the shift register unit in the k-th stage is connected to a signal output terminal of the shift register unit in a (k−1)-th stage via a third switching transistor corresponding to the k-th stage and further connected to an output terminal of the shift register unit in a (k−2)-th stage via a fourth switching transistor corresponding to the k-th stage. ### Claim 2 (depends on 1) The gate driving circuit according to claim 1, wherein the shift register unit in a first stage and the shift register unit in a second stage are configured as dummy shift register units; a signal output terminal of the shift register unit in the first stage is connected to a signal input terminal of the shift register unit in the second stage via the first switching transistor corresponding to the first stage, and a signal input terminal of the shift register unit in the first stage is configured to receive a frame start signal STV; and the signal input terminal of the shift register unit in the second stage is further configured to receive the frame start signal STV via the second switching transistor corresponding to the second stage. ### Claim 3 (depends on 1) The gate driving circuit according to claim 1, wherein a reset terminal of the shift register unit in a (2j−1)-th stage is connected to a signal output terminal of a stage shift register unit in a 2j-th stage via a fifth switching transistor corresponding to the (2j−1)-th stage and further connected to a signal output terminal of the shift register unit in a (2j+1)-th stage via a sixth switching transistor corresponding to the (2j−1)-th stage; and a reset terminal of the shift register unit in a 2j-th stage is connected to a signal output terminal of the shift register unit in the (2j+1)-th stage, where 1≤j≤(N−1)/2, and j is an integer. ### Claim 4 (depends on 1) A driving method applied to the gate driving circuit according to claim 1, comprising: in a 2D display mode, inputting a second voltage level to a first switching control line and inputting a first voltage level to a second switching control line, thereby turning on a first switching transistor disposed between two stages of GOA units that are immediately adjacent and turning off a second switching transistor disposed between two stages of GOA units that are spaced by one stage; inputting the second voltage level to a first control line and a third control line, and inputting the first voltage level to a second control line and a fourth control line, so that clock signals to be selected and output by two stages of GOA units that are immediately adjacent are a first clock signal and a second clock signal; and inputting a frame start signal to a signal input terminal of a dummy shift register unit in a first stage, and inputting the first clock signal and a second clock signal to the first clock signal terminal and the second clock signal terminal of the dummy shift register unit in the first stage, respectively, so that scanning shift register units in respective stages sequentially output driving signals to gate lines connected thereto. ### Claim 5 (depends on 4) The driving method according to claim 4, further comprising: in a 3D display mode, inputting the first voltage level to the first switching control line and inputting the second voltage level to the second switching control line, thereby turning off the first switching transistor disposed between two stages of GOA units that are immediately adjacent and turning on the second switching transistor disposed between two stages of GOA units that are spaced by one stage; inputting the second voltage level to the first control line and the fourth control line, and inputting the first voltage level to the second control line and the third control line, so that clock signals to be selected and output by every two stages of GOA units that are immediately adjacent are the same, being one of a first clock signal and a second clock signal, and the clock signal to be selected and output by two stages of GOA units subsequent thereto is the other one of the first clock signal and the second clock signal; and inputting the frame start signal to a signal input terminal of the dummy shift register unit in first and second stages, and inputting the first clock signal and the second clock signal to the first clock signal terminal and the second clock signal terminal of the dummy shift register unit in the first stage, respectively, so that timings of the signals received at the signal input terminals of every two stages of shift register units that are immediately adjacent are the same, and timings of the signals outputted therefrom are the same. ### Claim 6 (depends on 1) The gate driving circuit according to claim 1, wherein the shift register unit further comprises: a pull-down node control sub-circuit connected to the pull-up node and a second output terminal of the clock signal selection sub-circuit, and configured to control a voltage level at a pull-down node according to the first clock signal or the second clock signal provided by the clock signal selection sub-circuit and the voltage level at the pull-up node; and a pull-down sub-circuit connected to the pull-down node, the pull-up node, and the signal output terminal, and configured to pull down the pull-up node and the signal output terminal according to the voltage level at the pull-down node. ### Claim 7 (depends on 1) The gate driving circuit according to claim 1, wherein the shift register unit further comprises: an auxiliary control sub-circuit connected to the pull-up node, the signal output terminal, and a second output terminal of the clock signal selection sub-circuit, and configured to assist in controlling voltage levels at the pull-up node and the signal output terminal according to a clock signal provided by the clock signal selection sub-circuit. ### Claim 8 (depends on 1) The gate driving circuit according to claim 1, wherein, the input sub-circuit comprises: an input transistor having a control electrode and a first electrode connected to the signal input terminal, and a second electrode connected to the pull-up node; the output sub-circuit comprises: an output transistor having a control electrode connected to the pull-up node, a first electrode connected to the first output terminal of the clock signal selection sub-circuit, and a second electrode connected to the signal output terminal; and a capacitor having a first terminal connected to the pull-up node, and a second terminal connected to the signal output terminal; and the reset sub-circuit comprises: a first reset transistor having a control electrode connected to the reset terminal, a first electrode connected to the pull-up node, and a second electrode connected to a first power supply terminal; and a second reset transistor having a control electrode connected to the reset terminal, a first electrode connected to the signal output terminal, and a second electrode connected to the first power supply terminal. ### Claim 9 (depends on 1) The gate driving circuit according to claim 1, wherein the clock signal selection sub-circuit comprises: a first selection transistor having a control electrode connected to the first control terminal, a first electrode connected to the first clock signal terminal, and a second electrode connected to the first output terminal of the clock signal selection sub-circuit; and a second selection transistor having a control electrode connected to the second control terminal, a first electrode connected to the second clock signal terminal, and a second electrode connected to the first output terminal of the clock signal selection sub-circuit. ### Claim 10 (depends on 9) The gate driving circuit according to claim 9, wherein the clock signal selection sub-circuit further comprises: a third selection transistor having a control electrode connected to the first control terminal, a first electrode connected to the second clock signal terminal, and a second electrode connected to a second output terminal of the clock signal selection sub-circuit; and a fourth selection transistor having a control electrode connected to the second control terminal, a first electrode connected to the first clock signal terminal, and a second electrode connected to the second electrode of the third selection transistor. ### Claim 11 (depends on 6) The gate driving circuit according to claim 6, wherein the pull-down node control sub-circuit comprises: a first pull-down control transistor having a control electrode and a first electrode connected to the second output terminal of the clock signal selection sub-circuit, and a second electrode connected to a pull-down control node; a second pull-down control transistor having a control electrode connected to the pull-down control node, a first electrode connected to the first electrode of the first pull-down control transistor, and a second electrode connected to the pull-down node; and a third pull-down control transistor having a control electrode connected to the pull-up node, a first electrode connected to the pull-down control node, and a second electrode connected to a first power supply terminal; and a fourth pull-down control transistor having a control electrode connected to the pull-up node, a first electrode connected to the pull-down node, and a second electrode connected to the first power supply terminal. ### Claim 12 (depends on 6) The gate driving circuit according to claim 6, wherein the pull-down sub-circuit comprises: a first pull-down transistor having a control electrode connected to the pull-down node, a first electrode connected to the pull-up node, and a second electrode connected to a first power supply terminal; and a second pull-down transistor having a control electrode connected to the pull-down node, a first electrode connected to the signal output terminal, and a second electrode connected to the first power supply terminal. ### Claim 13 (depends on 7) The gate driving circuit according to claim 7, wherein the auxiliary control sub-circuit comprises: a first auxiliary control transistor having a control electrode connected to the second output terminal of the clock signal selection sub-circuit, a first electrode connected to the signal input terminal, and a second electrode connected to the pull-up node; and a second auxiliary control transistor having a control electrode connected to the second output terminal of the clock signal selection sub-circuit, a first electrode connected to the signal output terminal, and a second electrode connected to a first power supply terminal. ### Claim 14 (depends on 6) The gate driving circuit according to claim 6, wherein the shift register unit further comprises: an auxiliary control sub-circuit connected to the pull-up node, the signal output terminal, and a second output terminal of the clock signal selection sub-circuit, and configured to assist in controlling voltage levels at the pull-up node and the signal output terminal according to a clock signal provided by the clock signal selection sub-circuit. ### Claim 15 (depends on 14) The gate driving circuit according to claim 14, wherein the clock signal selection sub-circuit comprises: a first selection transistor having a control electrode connected to the first control terminal, a first electrode connected to the first clock signal terminal, and a second electrode connected to the first output terminal of the clock signal selection sub-circuit; and a second selection transistor having a control electrode connected to the second control terminal, a first electrode connected to the second clock signal terminal, and a second electrode connected to the first output terminal of the clock signal selection sub-circuit. ### Claim 16 (depends on 15) The gate driving circuit according to claim 15, wherein the clock signal selection sub-circuit further comprises: a third selection transistor having a control electrode connected to the first control terminal, a first electrode connected to the second clock signal terminal, and a second electrode connected to a second output terminal of the clock signal selection sub-circuit; and a fourth selection transistor having a control electrode connected to the second control terminal, a first electrode connected to the first clock signal terminal, and a second electrode connected to the second electrode of the third selection transistor. ### Claim 17 (depends on 14) The gate driving circuit according to claim 14, wherein the auxiliary control sub-circuit comprises: a first auxiliary control transistor having a control electrode connected to the second output terminal of the clock signal selection sub-circuit, a first electrode connected to the signal input terminal, and a second electrode connected to the pull-up node; and a second auxiliary control transistor having a control electrode connected to the second output terminal of the clock signal selection sub-circuit, a first electrode connected to the signal output terminal, and a second electrode connected to a first power supply terminal.