# US 10,872,572 B2 · Gate driving circuit and method for controlling the same, and display apparatus

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- Number: US 10,872,572 B2
- Document ID: US10872572B2
- Status: Granted
- Kind: B2
- Application number: 16/556,960
- Filed: 2019-08-30
- Published: 2020-04-23
- Granted: 2020-12-22
- Earliest claimed: 2018-10-23
- Assignees: Boe Technology Group Co., Ltd.
- Applicants: BOE Technology Group Co., Ltd.
- Inventors: Guangliang Shang; Seungwoo Han; Lijun Yuan; Mingfu Han; Haoliang Zheng; Xing Yao; Zhenyu Zhang
- Web page: https://patentgrep.com/patent/US10872572B2

## CPC

- G09G 3/3266: Details of drivers for scan electrodes
- G09G 3/3275: Details of drivers for data electrodes
- G09G 3/3666: {with the matrix divided into sections}
- G09G 3/3674: {Details of drivers for scan electrodes}
- G09G 3/3685: {Details of drivers for data electrodes}
- G09G 2310/0202: Addressing of scan or signal lines
- G09G 2310/0221: with use of split matrices (G09G3/3644 and G09G3/3666 take precedence)
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2330/08: Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

The embodiments of the present disclosure provide a gate driving circuit and a method for controlling the same, and a display apparatus. The gate driving circuit includes: M decoding sub-circuits, wherein each of the M decoding sub-circuits has K signal input terminals and 2K signal output terminals, where K=N/M, M, N and K are positive integers, 4≤M<N, and K≥2, N signal input terminals of the M decoding sub-circuits are connected to receive N-bit address data, and each of the M decoding sub-circuits is configured to receive respective K-bit data in the N-bit address data at K signal input terminals thereof, and select one of the 2K signal output terminals thereof which matches the received K-bit data; and a plurality of driving sub-circuits, wherein each of the plurality of driving sub-circuits is connected to M signal output terminals belonging to the M decoding sub-circuits respectively according to an address allocated thereto, and is configured to output a row driving signal when the M signal output terminals connected to the driving sub-circuit are all selected.

## Claims

### Claim 1

A gate driving circuit, comprising:
M decoding sub-circuits, wherein each of the M decoding sub-circuits has K signal input terminals and 2K signal output terminals, where K=N/M, M, N and K are positive integers, 4≤M<N, and K≥2, N signal input terminals of the M decoding sub-circuits are connected to receive N-bit address data, and each of the M decoding sub-circuits is configured to receive respective K-bit data in the N-bit address data at K signal input terminals thereof, and select one of the 2K signal output terminals thereof which matches the received K-bit data; and
a plurality of driving sub-circuits, wherein each of the plurality of driving sub-circuits is connected to M signal output terminals belonging to the M decoding sub-circuits respectively according to an address allocated thereto, and is configured to output a row driving signal when the M signal output terminals connected to the driving sub-circuit are all selected.

### Claim 2 (depends on 1)

The gate driving circuit according to claim 1, wherein the decoding sub-circuit comprises:
K inverters, wherein each of the K inverters has an input terminal connected to a respective one of the K signal input terminals, and is configured to invert a signal at an input terminal thereof and output the inverted signal at an output terminal thereof; and
2K logic gates, wherein each of the 2K logic gates has K input terminals connected to K inverters respectively with each of the K input terminals being connected to an input terminal or output terminal of a respective one of the K inverters, and an output terminal acting as one of the 2K signal output terminals of the decoding sub-circuit, and each of the logic gates is configured to output, to the output terminal thereof, a valid signal indicating that the output terminal is selected or an invalid signal indicating that the output terminal is not selected according to signals at K input terminals of the logic gate.

### Claim 3 (depends on 2)

The gate driving circuit according to claim 2, wherein the logic gate comprises at least one of a NAND gate, a NOR gate, an AND gate or an OR gate.

### Claim 4 (depends on 2)

The gate driving circuit according to claim 2, wherein N=8, M=4, K=2, the K inverters comprises a first inverter and a second inverter, and the 2K logic gates comprise a first NAND gate, a second NAND gate, a third NAND gate, and a fourth NAND gate, wherein
an input terminal of the first inverter is connected to one of two signal input terminals of the decoding sub-circuit;
an input terminal of the second inverter is connected to the other of the two signal input terminals;
the first NAND gate has a first input terminal connected to an output terminal of the first inverter, a second input terminal connected to an output terminal of the second inverter, and an output terminal acting as a first signal output terminal of the decoding sub-circuit;
the second NAND gate has a first input terminal connected to an input terminal of the first inverter, a second input terminal connected to the output terminal of the second inverter, and an output terminal acting as a second signal output terminal of the decoding sub-circuit;
the third NAND gate has a first input terminal connected to the output terminal of the first inverter, a second input terminal connected to the input terminal of the second inverter, and an output terminal acting as a third signal output terminal of the decoding sub-circuit; and
the fourth NAND gate has a first input terminal connected to the input terminal of the first inverter, a second input terminal connected to the input terminal of the second inverter, and an output terminal acting as a fourth signal output terminal of the decoding sub-circuit.

### Claim 5 (depends on 1)

The gate driving circuit according to claim 1, wherein the driving sub-circuit comprises:
an input sub-circuit connected to one of the 2K signal output terminals of each of the decoding sub-circuits and configured to provide a transmission control signal when the signal output terminals connected to the input sub-circuit are all selected;
a display control sub-circuit connected to the input sub-circuit, a clock signal terminal, and a display control terminal, and configured to perform a logic operation on signals at the clock signal terminal and the display control terminal under control of the transmission control signal from the input sub-circuit; and
a first power amplification sub-circuit connected to the display control sub-circuit and configured to amplify a result of the logical operation of the display control sub-circuit and output the amplified result as a first row driving signal.

### Claim 6 (depends on 5)

The gate driving circuit according to claim 5, wherein the input sub-circuit comprises:
a NOR gate having M input terminals connected to the M decoding sub-circuits respectively, wherein each of the M input terminals is connected to a respective one of signal output terminals of a respective decoding sub-circuit; and
a third inverter having an input terminal connected to an output terminal of the NOR gate, and an output terminal connected to the display control sub-circuit to provide the transmission control signal to the display control sub-circuit.

### Claim 7 (depends on 5)

The gate driving circuit according to claim 5, wherein the display control sub-circuit comprises:
a transmission gate having a control terminal connected to the input sub-circuit to receive the transmission control signal, and an input terminal connected to the clock signal terminal;
a fifth NAND gate having a first input terminal connected to an output terminal of the transmission gate, and a second input terminal connected to the display control terminal; and
a fourth inverter having an input terminal connected to the output terminal of the fifth NAND gate, and an output terminal connected to the first power amplification sub-circuit.

### Claim 8 (depends on 7)

The gate driving circuit according to claim 7, wherein the first power amplification sub-circuit comprises:
a fifth inverter having an input terminal connected to the output terminal of the fourth inverter; and
a sixth inverter having an input terminal connected to the output terminal of the fifth inverter, and an output terminal acting as a first output terminal of the driving sub-circuit for outputting the first row driving signal.

### Claim 9 (depends on 8)

The gate driving circuit according to claim 8, wherein a size of each of the fifth inverter and the sixth inverter is greater than that of the fourth inverter.

### Claim 10 (depends on 5)

The gate driving circuit according to claim 5, wherein the driving sub-circuit further comprises: a second power amplification sub-circuit connected to the display control sub-circuit, and configured to amplify the result of the logical operation of the display control sub-circuit and output the amplified result as a second row driving signal.

### Claim 11 (depends on 10)

The gate driving circuit according to claim 10, wherein
the first row driving signal is at a high level, and the second row driving signal is at a low level; or
the first row driving signal is at a low level, and the second row driving signal is at a low level.

### Claim 12 (depends on 10)

The gate driving circuit according to claim 10, wherein the second power amplification sub-circuit comprises: a seventh inverter having an input terminal connected to the display control sub-circuit to receive the result of the logical operation from the display control sub-circuit, and an output terminal acting as a second output terminal of the driving sub-circuit for outputting the second row driving signal.

### Claim 13 (depends on 12)

The gate driving circuit according to claim 12, wherein a size of the seventh inverter is greater than that of the fourth inverter.

### Claim 14 (depends on 1)

A display apparatus, comprising the gate driving circuit according to claim 1.

### Claim 15 (depends on 1)

A method for controlling the gate driving circuit according to claim 1, comprising:
receiving, by each of the M decoding sub-circuits, respective K-bit data in N-bit address data and selecting one of the 2K signal output terminals of the decoding sub-circuit which matches the received K-bit data; and
outputting, by one of the plurality of driving sub-circuits connected to a plurality of signal output terminals which are all selected, a row driving signal.

### Claim 16 (depends on 15)

The method according to claim 15, wherein
the decoding sub-circuit comprises K inverters and 2K logic gates, wherein each of the inverters has an input terminal connected to a respective one of the K signal input terminals, and is configured to invert a signal at the input terminal thereof and output the inverted signal at an output terminal thereof, each of the logic gates has K input terminals connected to K inverters respectively with each of the K input terminals being connected to an input terminal or output terminal of a respective one of the K inverters, and an output terminal acting as one of the 2K signal output terminals of the decoding sub-circuit; and
receiving respective K-bit data in the N-bit address data and selecting one of the 2K signal output terminals of the decoding sub-circuit which matches the received K-bit data comprises:
inverting, by each inverter, a signal at an input terminal thereof and outputting the inverted signal at an output terminal thereof; and
outputting, by each of the logic gates, to an output terminal thereof, a valid signal indicating that the output terminal is selected or an invalid signal indicating that the output terminal is not selected, according to signals at K input terminals of the logic gate.

### Claim 17 (depends on 15)

The method according to claim 15, wherein the driving sub-circuit comprises an input sub-circuit, a display control sub-circuit, and a first power amplification sub-circuit, and outputting, by one of the plurality of driving sub-circuits connected a plurality of signal output terminals which are all selected, a row driving signal comprises:
providing, by the input sub-circuit, a transmission control signal to the display control sub-circuit when the plurality of signal output terminals connected to the input sub-circuit output a valid signal;
performing, by the display control sub-circuit, a logic operation on signals at the clock signal terminal and the display control terminal under control of the transmission control signal, and transmitting a result of the logical operation to the first power amplification sub-circuit; and
amplifying, by the first power amplification sub-circuit, the result of the operation output by the display control sub-circuit and outputting the amplified result as a first row driving signal.

### Claim 18 (depends on 17)

The method according to claim 17, wherein the driving sub-circuit further comprises a second power amplification sub-circuit, and the method further comprises:
transmitting, by the display control sub-circuit, the result of the logical operation to the second power amplification sub-circuit; and
amplifying, by the second power amplification sub-circuit, the result of the logical operation of the display control sub-circuit and outputting the amplified result as a second row driving signal.

### Claim 19 (depends on 17)

The method according to claim 17, wherein
the first row driving signal is at a high level, and the second row driving signal is at a low level; or
the first row driving signal is at a low level, and the second row driving signal is at a low level.