# US 10,872,546 B2 · Shift register unit and method for driving the same, gate driving circuit and display apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,546 B2 - Document ID: US10872546B2 - Status: Granted - Kind: B2 - Application number: 16/114,545 - Filed: 2018-08-28 - Published: 2019-08-15 - Granted: 2020-12-22 - Earliest claimed: 2018-02-12 - Assignees: Boe Technology Group Co., Ltd.; Hefei Boe Optoelectronics Technology Co., Ltd. - Applicants: BOE Technology Group Co., Ltd.; Hefei BOE Optoelectronics Technology Co., Ltd. - Inventors: Wei Xue; Jian Tao; Hongmin Li; Ying Wang - Web page: https://patentgrep.com/patent/US10872546B2 ## CPC - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 3/3677: {suitable for active matrices only} - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G11C 19/287: {Organisation of a multiplicity of shift registers} - G09G 2300/0809: Several active elements per pixel in active matrix panels - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract The embodiments of the present application disclose a shift register unit and a method for driving the same, a gate driving circuit and a method for driving the same, and a display apparatus. The shift register unit comprises an input sub-circuit connected to an input signal terminal and a pull-up control node, and configured to charge the pull-up control node under control of an input signal; and an output sub-circuit connected to the pull-up control node, a clock signal terminal, a first voltage terminal, and an output signal terminal, and configured to output a first constant voltage to the output signal terminal under control of a clock signal and the pull-up control node. ## Claims ### Claim 1 A shift register unit, comprising an input signal terminal configured to receive an input signal, a clock signal terminal configured to receive a clock signal, a first voltage terminal configured to receive a first constant voltage, a second voltage terminal configured to receive a second voltage signal, a third voltage terminal configured to receive a third voltage signal, an output signal terminal configured to output a gate control signal, and a reset signal terminal configured to receive a reset signal, the shift register unit further comprising: an input sub-circuit connected to the input signal terminal and a pull-up control node, and configured to charge the pull-up control node under control of the input signal; an output sub-circuit connected to the pull-up control node, the clock signal terminal, the first voltage terminal, and the output signal terminal, and configured to output the first constant voltage to the output signal terminal under control of the clock signal and the pull-up control node; and a reset sub-circuit connected to the pull-up control node, the reset signal terminal, and the third voltage terminal respectively, and configured to reset the pull-up control node to the third voltage under control of the reset signal, wherein the output sub-circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor, and a second capacitor, wherein: the first transistor has a gate connected to the clock signal terminal, a first electrode connected to the pull-up control node, and a second electrode connected to a gate of the second transistor via a first node; the second transistor has a first electrode connected to the first voltage terminal, and a second electrode connected to the output signal terminal; the first capacitor has a first terminal connected to the output signal terminal, and a second terminal connected to the first node; the second capacitor has a first terminal connected to the pull-up control node, and a second terminal connected to the first terminal of the first capacitor; the third transistor has a gate connected to the input signal terminal, a first electrode connected to the second voltage terminal, and a second electrode connected to the first node; the fourth transistor has a gate connected to the reset signal terminal, a first electrode connected to the second voltage terminal, and a second electrode connected to the first node; and the fifth transistor has a gate connected to a pull-down control node, a first electrode connected to the second voltage terminal, and a second electrode connected to the output signal terminal. ### Claim 2 (depends on 1) The shift register unit according to claim 1, wherein the first capacitor has a capacitance value greater than that of the second capacitor. ### Claim 3 (depends on 1) The shift register unit according to claim 1, further comprising a fourth voltage terminal configured to receive a fourth voltage signal, a pull-up control sub-circuit, and a pull-down control sub-circuit, wherein the pull-up control sub-circuit is connected to the pull-up control node, the pull-down control node, and the second voltage terminal, and is configured to provide the second voltage signal from the second voltage terminal to the pull-up control node under control of the pull-down control node; and the pull-down control sub-circuit is connected to the pull-up control node, the pull-down control node, the second voltage terminal, and the fourth voltage terminal, and is configured to provide the second voltage signal or the fourth voltage signal to the pull-down control node under control of the pull-up control node and the fourth voltage signal. ### Claim 4 (depends on 3) The shift register unit according to claim 3, wherein the pull-up control sub-circuit comprises a sixth transistor having a gate connected to the pull-down control node, a first electrode connected to the pull-up control node, and a second electrode connected to the second voltage terminal; and the pull-down control sub-circuit comprises a seventh transistor and an eighth transistor, wherein the seventh transistor has a gate connected to the pull-up control node, a first electrode connected to the second voltage terminal, and a second electrode connected to the pull-down control node; and the eighth transistor has a gate and a first electrode connected to the fourth voltage terminal, and a second electrode connected to the pull-down control node. ### Claim 5 (depends on 1) The shift register unit according to claim 1, further comprising a fourth voltage terminal configured to receive a fourth voltage signal, a pull-up control sub-circuit, and a pull-down control sub-circuit, wherein the pull-up control sub-circuit is connected to the pull-up control node, the pull-down control node, and the second voltage terminal, and is configured to provide the second voltage signal from the second voltage terminal to the pull-up control node under control of the pull-down control node; and the pull-down control sub-circuit is connected to the pull-up control node, the pull-down control node, the second voltage terminal, and the fourth voltage terminal, and is configured to provide the second voltage signal or the fourth voltage signal to the pull-down control node under control of the pull-up control node and the fourth voltage signal. ### Claim 6 (depends on 5) The shift register unit according to claim 5, wherein the pull-up control sub-circuit comprises a sixth transistor having a gate connected to the pull-down control node, a first electrode connected to the pull-up control node, and a second electrode connected to the second voltage terminal; and the pull-down control sub-circuit comprises a seventh transistor and an eighth transistor, wherein the seventh transistor has a gate connected to the pull-up control node, a first electrode connected to the second voltage terminal, and a second electrode connected to the pull-down control node; and the eighth transistor has a gate and a first electrode connected to the fourth voltage terminal, and a second electrode connected to the pull-down control node. ### Claim 7 (depends on 1) The shift register unit according to claim 1, further comprising a fifth voltage terminal configured to receive a fifth voltage signal, wherein the input sub-circuit comprises a ninth transistor having a gate connected to the input signal terminal, a first electrode connected to the fifth voltage terminal, and a second electrode connected to the pull-up control node. ### Claim 8 (depends on 1) The shift register unit according to claim 1, wherein the reset sub-circuit comprises a tenth transistor having a gate connected to the reset signal terminal, a first electrode connected to the third voltage terminal, and a second electrode connected to the pull-up control node. ### Claim 9 (depends on 1) A gate driving circuit, comprising a plurality of cascaded shift register units according to claim 1, wherein the input signal terminal of a first stage of shift register unit and the reset signal terminal of a last stage of shift register unit are connected to a vertical starting signal line; the input signal terminal of each stage of shift register unit other than the first stage of shift register unit is connected to an output signal terminal of a previous stage of shift register unit; and the reset signal terminal of each stage of shift register unit other than the last stage of shift register unit is connected to an output signal terminal of a next stage of shift register unit. ### Claim 10 (depends on 9) A display apparatus, comprising the gate driving circuit according to claim 9. ### Claim 11 (depends on 1) A method for driving the shift register unit according to claim 1, comprising: in a first phase, charging the pull-up control node through the input sub-circuit under control of the input signal; in a second phase, transmitting the first constant voltage to the output signal terminal through the output sub-circuit under control of the pull-up control node and the clock signal; and in a third phase, resetting the pull-up control node and the first node to a first level under control of the reset signal. ### Claim 12 (depends on 11) The method according to claim 11, wherein the first constant voltage has a valid level and the first level is an invalid level. ### Claim 13 (depends on 9) A method for driving the gate driving circuit according to claim 9, comprising: providing a vertical starting signal to the input signal terminal of the first stage of shift register unit and the reset signal terminal of the last stage of shift register unit; and providing a fifth voltage having a valid level and a third voltage having an invalid level. ### Claim 14 (depends on 9) A method for driving the gate driving circuit according to claim 9, comprising: providing a vertical starting signal to the input signal terminal of the first stage of shift register unit and the reset signal terminal of the last stage of shift register unit; and providing a fifth voltage having an invalid level and a third voltage having a valid level. ### Claim 15 (depends on 9) A method for driving the gate driving circuit according to claim 9, comprising: providing a vertical starting signal to the input signal terminal of the first stage of shift register unit and the reset signal terminal of the last stage of shift register unit; providing, in odd-numbered frames, a fifth voltage having a valid level and a third voltage having an invalid level; and providing, in even-numbered frames, a fifth voltage having an invalid level and a third voltage having a valid level. ### Claim 16 (depends on 9) A method for driving the gate driving circuit according to claim 9, comprising: providing a vertical starting signal to the input signal terminal of the first stage of shift register unit and the reset signal terminal of the last stage of shift register unit; providing, in odd-numbered frames, a fifth voltage having an invalid level and a third voltage having a valid level; and providing, in even-numbered frames, a fifth voltage having a valid level and a third voltage having an invalid level.