# US 10,872,186 B2 · Tool to create a reconfigurable interconnect framework

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- Number: US 10,872,186 B2
- Document ID: US10872186B2
- Status: Granted
- Kind: B2
- Application number: 16/549,485
- Filed: 2019-08-23
- Published: 2019-12-12
- Granted: 2020-12-22
- Earliest claimed: 2017-01-04
- Assignees: STMicroelectronics S.r.l.; STMicroelectronics International N.V.
- Applicants: Stmicroelectronics S.R.L.; Stmicroelectronics International N.V.
- Inventors: Thomas Boesch; Giuseppe Desoli
- Web page: https://patentgrep.com/patent/US10872186B2

## CPC

- G06N 3/0464: Convolutional networks [CNN, ConvNet]
- G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
- G06F 30/34: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- G06F 30/347: Physical level, e.g. placement or routing
- G06N 3/045: Combinations of networks
- G06N 3/0495: Quantised networks; Sparse networks; Compressed networks
- G06N 3/084: Backpropagation, e.g. using gradient descent
- G06N 20/00: Machine learning
- G06N 20/10: using kernel methods, e.g. support vector machines [SVM]
- G06F 9/44505: {Configuring for program initiating, e.g. using registry, configuration files}
- G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)}
- G06F 15/7817: {Specially adapted for signal processing, e.g. Harvard architectures}
- G06F 2115/02: System on chip [SoC] design
- G06F 2115/08: Intellectual property [IP] blocks or IP cores
- G06N 3/044: Recurrent networks, e.g. Hopfield networks
- G06N 3/047: Probabilistic or stochastic networks
- G06N 3/063: using electronic means
- G06N 7/01: Probabilistic graphical models, e.g. probabilistic networks
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Embodiments are directed towards a method to create a reconfigurable interconnect framework in an integrated circuit. The method includes accessing a configuration template directed toward the reconfigurable interconnect framework, editing parameters of the configuration template, functionally combining the configuration template with a plurality of modules from an IP library to produce a register transfer level (RTL) circuit model, generating at least one automated test-bench function, and generating at least one logic synthesis script. Editing parameters of the configuration template includes confirming a first number of output ports of a reconfigurable stream switch and confirming a second number of input ports of the reconfigurable stream switch. Each output port and each input port has a respective architectural composition. The output port architectural composition is defined by a plurality of N data paths including A data outputs and B control outputs. The input port architectural composition is defined by a plurality of M data paths including A data inputs and B control inputs.

## Claims

### Claim 1

A system, comprising:
a computing server;
a database communicatively coupled to the computing server; and
at least one memory communicatively coupled to the computing server, the at least one memory storing a user-editable configuration template, the configuration template defining parameters including:
a first number of reconfigurable stream switch output ports, each output port having an output port architectural composition, wherein the output port architectural composition is defined by a plurality of N data paths, the plurality of N data paths including A data outputs and B control outputs, wherein N, A, and B are non-zero integers; and
a second number of reconfigurable stream switch input ports, each input port having an input port architectural composition, wherein the input port architectural composition is defined by a plurality of M data paths, the plurality of M data paths including A data inputs and B control inputs, wherein the computing server, in operation, generates a register transfer level (RTL) circuit model including a model of a reconfigurable interconnect framework based on the stored user-editable configuration template.

### Claim 2 (depends on 1)

The system of claim 1 wherein the computing server, in operation:
simulates circuitry based on the RTL circuit model.

### Claim 3 (depends on 1)

The system of claim 1 wherein the computing server, in operation:
combines the user-edited configuration template with a plurality of modules from a logic block (IP) library to produce the RTL circuit model.

### Claim 4 (depends on 3)

The system of claim 3, comprising:
integrated circuit fabrication machinery coupled to the computing server, wherein the integrated circuit fabrication machinery, in operation, fabricates a reconfigurable interconnect framework based on the RTL circuit model.

### Claim 5 (depends on 3)

The system of claim 3 wherein the user-editable configuration template defines parameters of an accelerator framework and the RTL circuit model includes a model of an accelerator framework based on the stored user-editable configuration template.

### Claim 6 (depends on 5)

The system of claim 5 wherein the accelerator framework is a kernel accelerator framework.

### Claim 7 (depends on 5)

The system of claim 5 wherein the accelerator framework is a pre-processing accelerator framework.

### Claim 8 (depends on 5)

The system of claim 5 wherein the accelerator framework is a neural accelerator framework.

### Claim 9 (depends on 5)

The system of claim 5 wherein the accelerator framework is a convolutional accelerator framework.

### Claim 10 (depends on 1)

The system of claim 1 wherein the RTL circuit model is a model of a system on a chip (SoC) including the reconfigurable interconnect framework model.

### Claim 11 (depends on 10)

The system of claim 10 wherein the SoC model includes a model of smartphone circuitry.

### Claim 12

A method, comprising:
accessing, using processing circuitry, a configuration template of a reconfigurable interconnect framework;
editing, using the processing circuitry, parameters of the configuration template, the editing including:
setting a first number of output ports of a reconfigurable stream switch, each output port having an output port architectural composition, wherein the output port architectural composition is defined by a plurality of N data paths, the plurality of N data paths including A data outputs and B control outputs, wherein N, A, and B are non-zero integers; and
setting a second number of input ports of the reconfigurable stream switch, each input port having an input port architectural composition, wherein the input port architectural composition is defined by a plurality of M data paths, the plurality of M data paths including A data inputs and B control inputs; and
functionally combining, using the processing circuitry, the configuration template with a plurality of modules from a logic block (IP) library to produce a register transfer level (RTL) circuit model including a model of a reconfigurable interconnect framework.

### Claim 13 (depends on 12)

The method of claim 12 wherein the configuration template defines parameters of an accelerator framework, the editing includes setting the parameters of the accelerator framework, and the RTL circuit model includes a model of an accelerator framework.

### Claim 14 (depends on 12)

The method of claim 12 wherein the accelerator framework includes one or more of a kernel accelerator framework, a pre-processing accelerator framework, a neural accelerator framework or a convolutional accelerator framework.

### Claim 15 (depends on 12)

The method of claim 12 wherein editing parameters of the configuration template comprises:
setting a number of external device interfaces; and
setting a communication protocol for at least some of the selected number of external device interfaces.

### Claim 16 (depends on 12)

The method of claim 12 wherein editing parameters of the configuration template comprises:
setting a number of processing modules; and
setting operational parameter of at least some of the number of processing modules.

### Claim 17 (depends on 12)

The method of claim 12, comprising:
performing at least one automated test-bench function on the RTL circuit model.

### Claim 18 (depends on 13)

The method of claim 13, comprising:
fabricating an integrated circuit including a reconfigurable interconnect framework and an accelerator framework based on the RTL circuit model.

### Claim 19

A non-transitory computer-readable medium storing computer-executable instructions, which when executed by one or more processing devices cause the one or more processing devices to perform a method, the method comprising:
accessing a configuration template of a reconfigurable interconnect framework;
editing parameters of the configuration template, the editing including:
setting a first number of output ports of a reconfigurable stream switch, each output port having an output port architectural composition, wherein the output port architectural composition is defined by a plurality of N data paths, the plurality of N data paths including A data outputs and B control outputs, wherein N, A, and B are non-zero integers; and
setting a second number of input ports of the reconfigurable stream switch, each input port having an input port architectural composition, wherein the input port architectural composition is defined by a plurality of M data paths, the plurality of M data paths including A data inputs and B control inputs; and
functionally combining, using the processing circuitry, the configuration template with a plurality of modules from a logic block (IP) library to produce a register transfer level (RTL) circuit model including a model of a reconfigurable interconnect framework.

### Claim 20 (depends on 19)

The non-transitory computer-readable medium of claim 19 wherein the configuration template defines parameters of an accelerator framework, the editing includes setting the parameters of the accelerator framework, and the RTL circuit model includes a model of an accelerator framework.

### Claim 21 (depends on 20)

The non-transitory computer-readable medium of claim 20 wherein the method comprises:
fabricating an integrated circuit including a reconfigurable interconnect framework and an accelerator framework based on the RTL circuit model.

### Claim 22 (depends on 1)

The system of claim 1 wherein the parameters of the configuration template include stream link configuration parameters, which define a reconfigurable stream switch output port associated with a stream link and one or more reconfigurable stream switch input ports associated with the stream link.

### Claim 23 (depends on 22)

The system of claim 22 wherein the stream link configuration parameters associated with the stream link define a number of communication paths of the stream link and a direction of each communication path.

### Claim 24 (depends on 12)

The method of claim 12 wherein the parameters of the configuration template include stream link configuration parameters, which define a reconfigurable stream switch output port associated with a stream link and one or more reconfigurable stream switch input ports associated with the stream link.

### Claim 25 (depends on 24)

The method of claim 24 wherein the stream link configuration parameters associated with the stream link define a number of communication paths of the stream link and a direction of each communication path.