# US 10,872,056 B2 · Remote memory access using memory mapped addressing among multiple compute nodes

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- Number: US 10,872,056 B2
- Document ID: US10872056B2
- Status: Granted
- Kind: B2
- Application number: 16/542,952
- Filed: 2019-08-16
- Published: 2019-12-05
- Granted: 2020-12-22
- Earliest claimed: 2016-06-06
- Assignees: Cisco Technology, Inc.
- Applicants: Cisco Technology, Inc.
- Inventors: Sagar Borikar
- Web page: https://patentgrep.com/patent/US10872056B2

## CPC

- G06F 15/17331: {Distributed shared memory [DSM], e.g. remote direct memory access [RDMA]}
- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- H04L 67/1097: for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
- H04L 67/133: Protocols for remote procedure calls [RPC]
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

An example method for facilitating remote memory access with memory mapped addressing among multiple compute nodes is executed at an input/output (IO) adapter in communication with the compute nodes over a Peripheral Component Interconnect Express (PCIE) bus, the method including: receiving a memory request from a first compute node to permit access by a second compute node to a local memory region of the first compute node; generating a remap window region in a memory element of the IO adapter, the remap window region corresponding to a base address register (BAR) of the second compute node; and configuring the remap window region to point to the local memory region of the first compute node, wherein access by the second compute node to the BAR corresponding with the remap window region results in direct access of the local memory region of the first compute node by the second compute node.

## Claims

### Claim 1

A method comprising: receiving, by a firmware, from a second node a message indicating an intent to read contents of a memory region of a first node; identifying, by the firmware, a first virtualized Network Interface Cards (VNICs) for the first node and a second VNIC for the second node; sending, by the firmware, a notification to the first VNIC of the intent to read contents of a memory of a first node; receiving, by the firmware through a memory request, from the first node an address of the memory region; sending, by the firmware, remap window region information to a Base Address Registry (BAR) field of the second node; mapping, by the firmware, the received address of the memory region of first node into the BAR field of the second VNIC; and sending, from the second VNIC to the second node, the remap window information.

### Claim 2 (depends on 1)

The method of claim 1, further comprising: identifying, prior to receiving the message indicating the intent to read contents of the memory region of the first node, a resource layout from a resource map, the resource layout include at least the first and second nodes.

### Claim 3 (depends on 2)

The method of claim 2, further comprising: providing, prior to the identifying the resource layout, the resource map.

### Claim 4 (depends on 1)

The method of claim 1, further comprising after the third sending:
accessing, at the second node, data from a BAR field of the second node that corresponds to the memory region of the first node.

### Claim 5 (depends on 4)

The method of claim 4, wherein the access is a read access.

### Claim 6 (depends on 4)

The method of claim 4, wherein the access is a write access.

### Claim 7 (depends on 1)

The method of claim 1, wherein the first and second compute nodes comprise microservers executing in a single chassis.

### Claim 8

A non-transitory computer readable media comprising instructions which when execute by a processor cause the processor to perform operations, comprising: receiving, by a firmware, from a second node a message indicating an intent to read contents of a memory region of a first node; identifying, by the firmware, a first virtualized Network Interface Cards (VNICs) for the first node and a second VNIC for the second node; sending, by the firmware, a notification to the first VNIC of the intent to read contents of a memory of a first node; receiving, by the firmware through a memory request, from the first node an address of the memory region; sending, by the firmware, remap window region information to a Base Address Registry (BAR) field of the second node; mapping, by the firmware, the received address of the memory region of first node into the BAR field of the second VNIC; and sending, from the second VNIC to the second node, the remap window information.

### Claim 9 (depends on 8)

The media of claim 8, the operations further comprising: identifying, prior to receiving the message indicating the intent to read contents of the memory region of the first node, a resource layout from a resource map, the resource layout include at least the first and second nodes.

### Claim 10 (depends on 9)

The media of claim 9, the operations further comprising: providing, prior to identifying the resource layout, the resource map.

### Claim 11 (depends on 8)

The media of claim 8, the operations further comprising after the third sending:
accessing, at the second node, data from a BAR field of the second node that corresponds to the memory region of the first node.

### Claim 12 (depends on 11)

The media of claim 11, wherein the access is a read access.

### Claim 13 (depends on 11)

The media of claim 11, wherein the access is a write access.

### Claim 14 (depends on 8)

The media of claim 8, wherein the first and second compute nodes comprise microservers executing in a single chassis.

### Claim 15

A system comprising: a processor; a non-transitory computer readable memory containing instructions which when executed by a processor cause the system to perform operations, comprising: receiving, by a firmware of the system, from a second node a message indicating an intent to read contents of a memory region of a first node; identifying, by the firmware, a first virtualized Network Interface Cards (VNICs) for the first node and a second VNIC for the second node; sending, by the firmware, a notification to the first VNIC of the intent to read contents of a memory of a first node; receiving, by the firmware through a memory request, from the first node an address of the memory region; sending, by the firmware, remap window region information to a BAR field of the second node; mapping, by the firmware, the received address of the memory region of first node into the BAR field of the second VNIC; and sending, from the second VNIC to the second node, the remap window information.

### Claim 16 (depends on 15)

The system of claim 15, the operations further comprising: identifying, prior to receiving the message indicating the intent to read contents of the memory region of the first node, a resource layout from a resource map, the resource layout include at least the first and second nodes.

### Claim 17 (depends on 16)

The system of claim 16, the operations further comprising: providing, prior to identifying resource layout, the resource map.

### Claim 18 (depends on 15)

The system of claim 15, the operations further comprising after the third sending:
accessing, at the second node, data from a BAR field of the second node that corresponds to the memory region of the first node.

### Claim 19 (depends on 18)

The system of claim 18, wherein the access is a read access.

### Claim 20 (depends on 18)

The system of claim 18, wherein the access is a write access.