# US 10,872,054 B2 · Wide programmable gain receiver data path for single-ended memory interface application > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,054 B2 - Document ID: US10872054B2 - Status: Granted - Kind: B2 - Application number: 16/661,081 - Filed: 2019-10-23 - Published: 2020-02-20 - Granted: 2020-12-22 - Earliest claimed: 2018-06-27 - Assignees: Integrated Device Technology, Inc. - Applicants: Integrated Device Technology, Inc. - Inventors: Yi Xie; Yue Yu; Yuan Zhang; Yu Min Zhang - Web page: https://patentgrep.com/patent/US10872054B2 ## CPC - G06F 13/4234: {being a memory bus} - G06F 13/4068: {Electrical coupling} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An apparatus includes an interface and a plurality of impedance branches. The interface may be configured to receive a data signal and a plurality of selection signals. The plurality of impedance branches may comprise a group of branches and a separated branch. The plurality of impedance branches may be configured to adjust an impedance value and a gain of a data path for the data signal in response to the selection signals. The group of branches may be controlled in response to the selection signals to select the impedance value and a first gain value in a first mode. The separated branch may replace one of the plurality of impedance branches in the group of branches in response to the selection signals to select a second gain value in a second mode. ## Claims ### Claim 1 An apparatus comprising: a memory interface implemented in a data path configured to receive a data signal and a plurality of selection signals; and a plurality of impedance branches (i) comprising a group of branches and a separated branch and (ii) configured to adjust an impedance value and a gain of said data path for said data signal in response to said selection signals, wherein (i) said group of branches are controlled in response to said selection signals to select said impedance value and a first gain value in a first mode, (ii) said separated branch replaces one of said plurality of impedance branches in said group of branches in response to said selection signals to select a second gain value in a second mode and (iii) said apparatus is configured to generate one component of a single input differential pair for both high gain values and low gain values. ### Claim 2 (depends on 1) The apparatus according to claim 1, wherein said selection signals comprise an enable signal, a first signal, a second signal and a swap signal. ### Claim 3 (depends on 2) The apparatus according to claim 2, wherein said swap signal selects between said first mode and said second mode. ### Claim 4 (depends on 2) The apparatus according to claim 2, wherein said impedance value is selected in response to said first signal and said second signal. ### Claim 5 (depends on 1) The apparatus according to claim 1, wherein said plurality of impedance branches are configured to adjust said impedance value to one of 60 Ohms, 120 Ohms, 240 Ohms and a high impedance state. ### Claim 6 (depends on 1) The apparatus according to claim 1, wherein said impedance value is a termination resistance for said data signal. ### Claim 7 (depends on 6) The apparatus according to claim 6, said termination resistance is selected to prevent signal reflections. ### Claim 8 (depends on 1) The apparatus according to claim 1, wherein said first gain value is 0 dB and said second gain value is −6 dB. ### Claim 9 (depends on 1) The apparatus according to claim 1, wherein said separated branch comprises an upper resistor and a lower resistor. ### Claim 10 (depends on 9) The apparatus according to claim 9, wherein (i) said upper resistor and said lower resistor provide a same resistance value and (ii) when said separated branch is activated, said gain is adjusted by −6 dB by implementing resistor division of said upper resistor and said lower resistor. ### Claim 11 (depends on 9) The apparatus according to claim 9, wherein said upper resistor and said lower resistor each provide a 120 Ohm resistance. ### Claim 12 (depends on 11) The apparatus according to claim 11, wherein said upper resistor and said lower resistor are combined to provide a 240 Ohm resistance when said separated branch is activated. ### Claim 13 (depends on 1) The apparatus according to claim 1, wherein said group of branches comprises four impedance branches, each providing a same resistance value. ### Claim 14 (depends on 1) The apparatus according to claim 1, wherein said apparatus realizes said gain for said data path while providing a same termination resistance in said first mode and in said second mode. ### Claim 15 (depends on 1) The apparatus according to claim 1, wherein (i) said plurality of impedance branches are configured in a parallel arrangement and (ii) said separated branch replaces one of said plurality of impedance branches in said group of branches by activating said separated branch and deactivating said one of said plurality of impedance branches. ### Claim 16 (depends on 1) The apparatus according to claim 1, wherein said apparatus is configured to communicate with a Continuous-Time Linear Estimation module. ### Claim 17 (depends on 16) The apparatus according to claim 16, wherein (i) a first gain range and a second gain range implement a gain from −6 dB to 6 dB, (ii) said apparatus is configured to implement said first gain range and (iii) said Continuous-Time Linear Estimation module is configured to implement said second gain range. ### Claim 18 (depends on 1) The apparatus according to claim 1, wherein each of said plurality of impedance branches and said separated branch each comprise a PMOS transistor configured to activate a resistance value in response to said selection signals. ### Claim 19 (depends on 1) The apparatus according to claim 1, further comprising a control logic configured to select from said impedance branches in response to said selection signals. ### Claim 20 An apparatus comprising: a memory interface implemented in a data path configured to receive a data signal and a plurality of selection signals; and a plurality of impedance branches (i) comprising a group of branches and a separated branch and (ii) configured to adjust an impedance value and a gain of said data path for said data signal in response to said selection signals, wherein (i) said group of branches are controlled in response to said selection signals to select said impedance value and a first gain value in a first mode, (ii) said separated branch replaces one of said plurality of impedance branches in said group of branches in response to said selection signals to select a second gain value in a second mode and (iii) said apparatus is configured to communicate with a Continuous-Time Linear Estimation module.