# US 10,872,051 B2 · Bus control circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,051 B2 - Document ID: US10872051B2 - Status: Granted - Kind: B2 - Application number: 16/561,328 - Filed: 2019-09-05 - Published: 2020-03-19 - Granted: 2020-12-22 - Earliest claimed: 2018-09-18 - Assignees: Canon Kabushiki Kaisha - Applicants: Canon Kabushiki Kaisha - Inventors: Kohei Murayama - Web page: https://patentgrep.com/patent/US10872051B2 ## CPC - G06F 13/362: with centralised access control - G06F 13/374: using a self-select method with individual priority code comparator - G06F 13/20: for access to input/output bus - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A bus control circuit comprises an arbitration circuit which receives a bus-transfer request from each of a plurality of bus masters and outputs an arbitration result signal, in accordance with a priority order, to one of the bus masters, and a plurality of bus switches, wherein each bus switch comprises a selection circuit which includes a plurality of input terminals for receiving a plurality of bus transfer signals and an output terminal for transmitting one bus transfer signal to a downstream side, and a control circuit which receives the arbitration result signal from the arbitration circuit and controls the selection circuit based on the arbitration result signal to select one of the plurality of input terminals, and a slave module is connected to the output terminal of the selection circuit in the bus switch located at a most downstream position. ## Claims ### Claim 1 A bus control circuit configured to control connection of a bus between a plurality of bus masters and a slave module, the circuit comprising: an arbitration circuit configured to receive a bus-transfer request signal from each of the plurality of bus masters and output an arbitration result signal representing that a bus-use right is to be given, in accordance with a priority order set in advance, to one of the bus masters that have issued the bus-transfer request signals; and a plurality of bus switches, wherein each of the plurality of bus switches comprises: a selection circuit including a plurality of input terminals configured to receive a plurality of bus transfer signals, respectively, and an output terminal configured to transmit one bus transfer signal of the received plurality of bus transfer signals to a downstream side; and a control circuit configured to receive the arbitration result signal output from the arbitration circuit and control the selection circuit based on the arbitration result signal to select the one bus transfer signal of the received plurality of bus transfer signals to be transmitted from the output terminal of the selection circuit to the downstream side, wherein the slave module is connected to the output terminal of the selection circuit included in the bus switch of the plurality of bus switches that is located at a most downstream position of the plurality of bus switches, and wherein the plurality of input terminals in the bus switch located at the most downstream position respectively receive the plurality of bus transfer signals from the output terminals of bus switches of the plurality of bus switches. ### Claim 2 (depends on 1) The circuit according to claim 1, wherein the control circuit includes a memory configured to convert the arbitration result signal into path information of the bus switch and hold the path information as a switching selection signal. ### Claim 3 (depends on 2) The circuit according to claim 2, wherein the memory included in the control circuit holds the switching selection signal in a FIFO form. ### Claim 4 (depends on 2) The circuit according to claim 2, wherein the control circuit determines whether the bus transfer signal is transferred via each of the plurality of bus switches, and converts the arbitration result signal into the path information of the bus switch. ### Claim 5 (depends on 4) The circuit according to claim 4, wherein upon determining that the bus transfer signal is transferred without an intervention of each of the plurality of bus switches, the control circuit does not perform processing responding to the arbitration result signal. ### Claim 6 (depends on 2) The circuit according to claim 2, wherein the path information is 1-bit information. ### Claim 7 (depends on 1) The circuit according to claim 1, wherein the bus switch includes a switch configured to transmit address information bus, and a switch configured to transmit data information bus. ### Claim 8 (depends on 1) The circuit according to claim 1, wherein the arbitration circuit further receives information representing a bus transfer direction from each of the plurality of bus masters together with the bus-transfer request signal, and outputs the information representing the bus transfer direction from the bus master decided to be given a bus-use right together with the arbitration result signal. ### Claim 9 (depends on 8) The circuit according to claim 8, wherein the control circuit includes a memory configured to convert the arbitration result signal and the information representing the bus transfer direction into path information of the bus switch and hold the path information as the switching selection signal. ### Claim 10 (depends on 1) The circuit according to claim 1, wherein the plurality of input terminals in each of the plurality of bus switches receive the plurality of bus transfer signals from at least one of the output terminals of the remaining bus switches and the plurality of bus masters. ### Claim 11 A bus control circuit configured to control connection of a bus between a plurality of bus masters and a slave module, the circuit comprising: an arbitration circuit configured to receive a bus-transfer request signal and information representing a bus transfer direction from each of the plurality of bus masters and output the information representing the bus transfer direction from the bus master decided to be given a bus-use right together with an arbitration result signal representing that the bus-use right is to be given, in accordance with a priority order set in advance, to one of the bus masters that have issued the bus-transfer request signals; and a plurality of bus switches, wherein each of the plurality of bus switches comprises: a selection circuit including a plurality of input terminals configured to receive a plurality of bus transfer signals, respectively, and an output terminal configured to transmit one bus transfer signal of the received plurality of bus transfer signals to a downstream side; and a control circuit configured to receive the arbitration result signal and the information representing the bus transfer direction output from the arbitration circuit, convert the arbitration result signal and the information representing the bus transfer direction into path information of the bus switch, hold the path information in a memory as a switching selection signal and control the selection circuit based on the switching selection signal to select the one bus transfer signal of the received plurality of bus transfer signals to be transmitted from the output terminal of the selection circuit to the downstream side, wherein the slave module is connected to the output terminal of the selection circuit included in the bus switch of the plurality of bus switches that is located at a most downstream position of the plurality of bus switches. ### Claim 12 A bus control circuit configured to control connection of a bus between a plurality of bus masters and a slave module, the circuit comprising: an arbitration circuit configured to receive a bus-transfer request signal from each of the plurality of bus masters and output an arbitration result signal representing that a bus-use right is to be given, in accordance with a priority order set in advance, to one of the bus masters that have issued the bus-transfer request signals; and a plurality of bus switches, wherein each of the plurality of bus switches comprises: a selection circuit including a plurality of input terminals configured to receive a plurality of bus transfer signals, respectively, and an output terminal configured to transmit one bus transfer signal of the received plurality of bus transfer signals to a downstream side; and a control circuit configured to receive the arbitration result signal output from the arbitration circuit, determine whether a bus transfer signal is transferred via each of the plurality of bus switches, convert the arbitration result signal into path information of the bus switch, hold the path information in a memory as a switching selection signal and control the selection circuit based on the arbitration result signal to select the one bus transfer signal of the received plurality of bus transfer signals to be transmitted from the output terminal of the selection circuit to the downstream side, wherein the slave module is connected to the output terminal of the selection circuit included in the bus switch of the plurality of bus switches that is located at a most downstream position of the plurality of bus switches, and wherein upon determining that the bus transfer signal is transferred without an intervention of each of the plurality of bus switches, the control circuit does not perform processing responding to the arbitration result signal.