# US 10,872,049 B2 · GPIO-to-GPIO communication on a multi-node daisy-chained network

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- Number: US 10,872,049 B2
- Document ID: US10872049B2
- Status: Granted
- Kind: B2
- Application number: 15/411,846
- Filed: 2017-01-20
- Published: 2017-08-03
- Granted: 2020-12-22
- Earliest claimed: 2016-01-29
- Assignees: Analog Devices, Inc.
- Applicants: Analog Devices, Inc.
- Inventors: Martin Kessler; William Hooper; Lewis F. Lahr
- Web page: https://patentgrep.com/patent/US10872049B2

## CPC

- G06F 13/364: using independent requests or grants, e.g. using separated request and grant lines
- G06F 13/404: {with address mapping}
- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Disclosed herein are systems and techniques for general purpose input/output (GPIO)-to-GPIO communication in a multi-node, daisy-chained network. In some embodiments, a transceiver may support GPIO between multiple nodes, without host intervention after initial programming. In some such embodiments, the host may be required only for initial setup of the virtual ports. In some embodiments, GPIO pins can be inputs (which may change virtual ports) or outputs (which may reflect virtual ports). In some embodiments, multiple virtual ports may be mapped to one GPIO output pin (with the values OR'ed together, for example). In some embodiments, multiple GPIO input pins may be mapped to one virtual port. For example, multiple GPIO input pin values may be OR'ed together, even if they come from multiple nodes.

## Claims

### Claim 1

A master node transceiver in a low latency communication system, comprising:
downstream transceiver circuitry to:
assign, over a bus to a downstream device, a virtual port identifier to a general purpose input/output (GPIO) pin of the downstream device, wherein the virtual port identifier identifies a virtual port, and
assign, over the bus to the downstream device, the GPIO pin to be an input pin or an output pin.

### Claim 2 (depends on 1)

The master node transceiver of claim 1, wherein the virtual port identifier includes an indication of a virtual port number associated with the GPIO pin.

### Claim 3 (depends on 2)

The master node transceiver of claim 2, wherein the downstream device is a first downstream device, the GPIO pin of the first downstream device is a first GPIO pin, and the downstream transceiver circuitry is further to:
assign, over the bus to a second downstream device different from the first downstream device, the virtual port identifier to a second GPIO pin of the second downstream device.

### Claim 4 (depends on 3)

The master node transceiver of claim 3, further comprising:
GPIO data circuitry to, when the first GPIO pin is an input pin and the second GPIO pin is an input pin, perform an OR logic operation on a value of the first GPIO pin and a value of the second GPIO pin to determine a value of the virtual port.

### Claim 5 (depends on 2)

The master node transceiver of claim 2, wherein the virtual port is a first virtual port, virtual port number is a first virtual port number, and the downstream transceiver circuitry is further to:
assign, over the bus to the downstream device, a second virtual port identifier to the GPIO pin of the downstream device, wherein the second virtual port identifier includes a second virtual port number different from the first virtual port number, and the second virtual port identifier identifies a second virtual port different from the first virtual port.

### Claim 6 (depends on 5)

The master node transceiver of claim 5, wherein the downstream device is to, when the GPIO pin is an output pin, perform an OR logic operation on a value of the first virtual port and a value of the second virtual port to determine a value of the GPIO pin.

### Claim 7 (depends on 1)

The master node transceiver of claim 1, wherein the downstream transceiver circuitry is further to:
transmit, over the bus to the downstream device, an instruction to set or clear the virtual port.

### Claim 8 (depends on 7)

The master node transceiver of claim 7, wherein the downstream device is a first downstream device, and the downstream transceiver circuitry is further to:
receive, over the bus from a second downstream device, a request to set or clear the virtual port;
wherein the downstream transceiver circuitry is to transmit the instruction to set or clear the virtual port in response to receipt of the request to set or clear the virtual port.

### Claim 9 (depends on 7)

The master node transceiver of claim 7, wherein the instruction is to clear the virtual port, and the master node transceiver further includes:
GPIO data circuitry to determine that at least one device downstream of the master node transceiver on the bus rejects the instruction, and, in response to the determination, maintain the virtual port as set in a memory of the master node transceiver.

### Claim 10 (depends on 9)

The master node transceiver of claim 9, wherein the determination includes identifying a not-acknowledge received from the at least one device downstream.

### Claim 11 (depends on 7)

The master node transceiver of claim 7, wherein the instruction is to set the virtual port, and the master node transceiver further includes:
GPIO data circuitry to set the virtual port in a memory of the master node transceiver.

### Claim 12 (depends on 1)

The master node transceiver of claim 1, further comprising:
host interface circuitry to communicatively couple the master node transceiver to a host device.

### Claim 13 (depends on 12)

The master node transceiver of claim 12, wherein the host interface circuitry includes Inter-Integrated Circuit (I2C) circuitry.

### Claim 14 (depends on 1)

The master node transceiver of claim 1, wherein the bus is a two-wire bus.

### Claim 15

A slave node transceiver in a low latency communication system, comprising:
upstream transceiver circuitry to:
receive, over a bus from a master node transceiver, an assignment of a virtual port identifier to a general purpose input/output (GPIO) pin of the slave node transceiver, wherein the virtual port identifier identifies a virtual port, and
receive, over the bus from the master node transceiver, an assignment of the GPIO pin as an input pin or an output pin.

### Claim 16 (depends on 15)

The slave node transceiver of claim 15, wherein the virtual port identifier includes an indication of a virtual port number associated with the GPIO pin, the GPIO pin is a first GPIO pin, and the upstream transceiver circuitry is further to:
receive, over the bus from the master node transceiver, an assignment of the virtual port identifier to a second GPIO pin of a downstream device, wherein the downstream device is downstream on the bus from the slave node transceiver.

### Claim 17 (depends on 16)

The slave node transceiver of claim 16, further comprising:
downstream transceiver circuitry to transmit, downstream over the bus, the assignment of the virtual port identifier to the second GPIO pin of the downstream device.

### Claim 18 (depends on 15)

The slave node transceiver of claim 15, further comprising:
GPIO data circuitry to invert a value of the GPIO pin.

### Claim 19 (depends on 15)

The slave node transceiver of claim 15, wherein the upstream transceiver circuitry is further to receive, from the master node transceiver over the bus, an instruction to change a value of the GPIO pin.

### Claim 20 (depends on 15)

The slave node transceiver of claim 15, wherein the GPIO pin is one of a plurality of GPIO pins of the slave node transceiver.