# US 10,872,047 B2 · Method and apparatus for processor standby

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- Number: US 10,872,047 B2
- Document ID: US10872047B2
- Status: Granted
- Kind: B2
- Application number: 16/042,912
- Filed: 2018-07-23
- Published: 2018-11-15
- Granted: 2020-12-22
- Earliest claimed: 2014-07-09
- Assignees: Advanced Micro Devices, Inc.
- Applicants: Advanced Micro Devices, Inc.
- Inventors: Greg Sadowski
- Web page: https://patentgrep.com/patent/US10872047B2

## CPC

- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G06F 1/3203: Power management, i.e. event-based initiation of a power-saving mode
- G06F 1/3287: by switching off individual functional units in the computer system
- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- Y02D 30/50: in wire-line communication networks, e.g. low power modes or reduced link rate
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A method of and device for removing a processor from a low power mode. The method includes and the device provides for performing multiple processor start-up tasks in parallel. Memory interface training between the processor and memory and restoration and initialization of the processor are performed in parallel with each other and with a serial bus controller entering serial bus training to facilitate communication between the processor and a system controller.

## Claims

### Claim 1

A method of holding a processor in a low power mode including:
storing context data in local memory controlled by and dedicated to the processor, context data indicating a desired state of the processor upon exiting the low power mode;
storing pointers to the context data in a system controller memory; and
maintaining a portion of the local volatile memory identified by the pointers while the processor is in the lower power mode.

### Claim 2 (depends on 1)

The method of claim 1, wherein the pointers indicate less than all of the local volatile memory dedicated to the processor.

### Claim 3 (depends on 1)

The method of claim 1, wherein the desired state of the processor is a last state of the processor prior to the processor entering the low power mode.

### Claim 4 (depends on 1)

The method of claim 1, wherein the context data is stored within multiple buffers of the local volatile memory, and wherein a startup sequence may utilize less than all of the buffers.

### Claim 5 (depends on 1)

The method of claim 1, wherein the context data further includes instructions regarding steps needed to be taken to take the processor out of the lower power mode.

### Claim 6

A method of placing a processor in a low power mode including:
storing processor state information in volatile memory controlled by and dedicated to the processor;
storing pointers to locations within the volatile memory where the state information is stored;
placing the volatile memory into a self-refresh mode;
engaging an external controller to facilitate the self-refresh mode of the volatile memory; and
placing the processor into a low power mode such that the processor is unable to facilitate the self-refresh mode.

### Claim 7 (depends on 6)

The method of claim 6, wherein the pointers are stored on a system controller.

### Claim 8 (depends on 6)

The method of claim 6, wherein the low power mode is a no power mode.

### Claim 9

A computing device including:
a processor;
a system controller;
a first volatile memory dedicated to the processor, the first volatile memory storing first information regarding a desired state for the processor;
a second memory storing data pointers to the first information, the second memory being accessible to the system controller; and
a controller operable to manage the refreshing of the first volatile memory while the processor is in a low power mode.

### Claim 10 (depends on 9)

The device of claim 9, wherein the controller is operable to cause a reset and clock enable signal to be supplied to the first volatile memory.

### Claim 11 (depends on 9)

The device of claim 9, wherein the reset and clock enable signals are supplied via state logic.

### Claim 12 (depends on 9)

The device of claim 9, wherein the controller is operable manage the refreshing of the first volatile memory by maintaining portions of the first memory identified by the data pointers while withholding maintenance signals from other portions of the first memory.

### Claim 13 (depends on 9)

The device of claim 9, wherein the computing device is a mobile computing device operable to be powered via battery.

### Claim 14 (depends on 9)

The device of claim 9 storing context data in the first volatile memory controlled by and dedicated to the processor, context data indicating a desired state of the processor upon exiting the low power mode;
storing pointers to the context data in the second memory; and
maintaining a portion of the first volatile memory identified by the pointers while the processor is in the lower power mode.

### Claim 15 (depends on 14)

The device of claim 14 wherein the pointers indicate less than all of the first volatile memory dedicated to the processor.

### Claim 16 (depends on 14)

The device of claim 14 wherein the desired state of the processor is a last state of the processor prior to the processor entering the low power mode.

### Claim 17 (depends on 14)

The device of claim 14 wherein the context data is stored within multiple buffers of the first volatile memory, and wherein a startup sequence may utilize less than all of the buffers.

### Claim 18 (depends on 14)

The device of claim 14 wherein the context data further includes instructions regarding steps needed to be taken to take the processor out of the lower power mode.