# US 10,872,009 B2 · Mitigating a voltage condition of a memory cell in a memory sub-system

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- Number: US 10,872,009 B2
- Document ID: US10872009B2
- Status: Granted
- Kind: B2
- Application number: 16/045,641
- Filed: 2018-07-25
- Published: 2019-08-08
- Granted: 2020-12-22
- Earliest claimed: 2018-02-08
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Vamsi Pavan Rayaprolu; Kishore Kumar Muchherla; Peter Feeley; Sampath K. Ratnam; Sivagnanam Parthasarathy; Qisong Lin; Shane Nowell; Mustafa N. Kaynak
- Web page: https://patentgrep.com/patent/US10872009B2

## CPC

- G11C 16/34: Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0634: {by changing the state or mode of one or more devices}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 11/073: {in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00)}
- G06F 11/076: {by exceeding a count or rate limit, e.g. word- or bit count limit}
- G06F 11/079: {Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36)}
- G06F 11/0793: {Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40)}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G11C 16/10: Programming or data input circuits
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written}
- G11C 16/3445: {Circuits or methods to verify correct erasure of nonvolatile memory cells}
- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- G11C 29/00: Checking stores for correct operation {; Subsequent repair}; Testing stores during standby or offline operation
- G11C 29/021: {in voltage or current generators}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 29/84: {with improved access time or stability}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 2029/0409: {Online test}
- G11C 2207/2272: Latency related aspects
- G11C 2207/2281: Timing of a read operation
- G11C 2207/229: Timing of a write operation
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A number of operations that have been performed on one or more memory cells that are proximate to a particular memory cell of the memory component can be identified. A determination as to whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate can be made based on the identified number of operations. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.

## Claims

### Claim 1

A system comprising:
a memory component; and
a processing device, operatively coupled with the memory component, to:
determine whether a particular memory cell of the memory component has transitioned from a state associated with a first error rate to another state associated with a second error rate based on a number of first operations that have been performed on one or more memory cells that are proximate to the particular memory cell, the second error rate corresponding to a higher number of errors than the first error rate; and
in response to determining that the particular memory cell has transitioned from the state associated with the first error rate to the another state associated with the second error rate, perform a second operation on the particular memory cell to transition the particular memory cell from the another state associated with the second error rate to the state associated with the first error rate.

### Claim 2 (depends on 1)

The system of claim 1, wherein the state associated with the first error rate corresponds to a transient threshold voltage state of the particular memory cell and the another state associated with the second error rate corresponds to a stable threshold voltage state of the particular memory cell, and wherein data stored at the particular memory cell is retrieved with fewer errors when the particular memory cell is at the transient threshold voltage state than when the particular memory cell is at the stable threshold voltage state.

### Claim 3 (depends on 1)

The system of claim 1, wherein to determine whether the particular memory cell has transitioned from the state associated with the first error rate to the another state associated with the second error rate based on the number of first operations, the processing device is further to:
determine whether the number of first operations that have been performed on the one or more memory cells is equal to or exceeds a threshold number of operations, wherein the particular memory cell is determined to have transitioned to the another state associated with the second error rate when the number of first operations is equal to or exceeds the threshold number of operations.

### Claim 4 (depends on 1)

The system of claim 1, wherein the second operation is a read operation or an application of a voltage.

### Claim 5 (depends on 1)

The system of claim 1, wherein the processing device is further to:
identify that a first programming operation has been performed on the particular memory cell and that a second programming operation has not been performed on the particular memory cell, wherein the performing of the second operation on the particular memory cell is further in response to the first programming operation being performed on the particular memory cell and the second programming operation not having been performed on the particular memory cell.

### Claim 6 (depends on 1)

The system of claim 1, wherein the one or more memory cells that are proximate to the particular memory cell are located on a same word line as the particular memory cell, wherein the one or more memory cells that are proximate to the particular memory cell correspond to a data block that is at a same plane of another data block that includes the particular memory cell.

### Claim 7 (depends on 1)

The system of claim 1, wherein the first operations that have been performed on the one or more memory cells are write operations or erase operations.

### Claim 8

A non-transitory computer readable medium comprising instructions that, when executed by a processing device, cause the processing device to:
determine whether a memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate;
receive a read offset corresponding to the another state associated with the increased error rate; and
in response to determining that the memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, perform a read operation on the memory cell based on the read offset corresponding to the another state associated with the increased error rate.

### Claim 9 (depends on 8)

The non-transitory computer readable medium of claim 8, wherein the state associated with the decreased error rate corresponds to a transient threshold voltage state of the memory cell and the another state associated with the increased error rate corresponds to a stable threshold voltage state of the memory cell, and wherein data stored at the memory cell is retrieved with fewer errors when the memory cell is at the transient threshold voltage state than when the memory cell is at the stable threshold voltage state.

### Claim 10 (depends on 8)

The non-transitory computer readable medium of claim 8, wherein the read offset specifies a threshold voltage to apply to the memory cell when performing the read operation to retrieve data stored at the memory cell.

### Claim 11 (depends on 8)

The non-transitory computer readable medium of claim 8, wherein the instructions further cause the processing device to:
in response to determining that the memory cell has not transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, perform the read operation on the memory cell without the read offset.

### Claim 12 (depends on 11)

The non-transitory computer readable medium of claim 11, wherein the read operation without the read offset and the read operation based on the read offset specify different threshold voltages to apply to the memory cell when performing the read operation.

### Claim 13 (depends on 8)

The non-transitory computer readable medium of claim 8, wherein the determining of whether the memory cell has transitioned is based on a number of operations performed on other memory cells or an amount of time that has elapsed since a programming operation was performed on the memory cell.

### Claim 14

A method comprising:
determining whether a particular memory cell of a memory component has transitioned from a state associated with a first error rate to another state associated with a second error rate based on a number of first operations that have been performed on one or more memory cells that are proximate to the particular memory cell, the second error rate corresponding to a higher number of errors than the first error rate; and
in response to determining that the particular memory cell has transitioned from the state associated with the first error rate to the another state associated with the second error rate, performing, by a processing device, a second operation on the particular memory cell to transition the particular memory cell from the another state associated with the second error rate to the state associated with the first error rate.

### Claim 15 (depends on 14)

The method of claim 14, wherein the state associated with the first error rate corresponds to a transient threshold voltage state of the particular memory cell and the another state associated with the second error rate corresponds to a stable threshold voltage state of the particular memory cell, and wherein data stored at the particular memory cell is retrieved with fewer errors when the particular memory cell is at the transient threshold voltage state than when the particular memory cell is at the stable threshold voltage state.

### Claim 16 (depends on 14)

The method of claim 14, wherein determining whether the particular memory cell has transitioned from the state associated with the first error rate to another state associated with the second error rate based on the number of first operations comprises:
determining whether the number of first operations that have been performed on the one or more memory cells is equal to or exceeds a threshold number of operations, wherein the particular memory cell is determined to have transitioned to the another state associated with the second error rate when the number of first operations is equal to or exceeds the threshold number of operations.