# US 10,871,992 B2 · Level two first-in-first-out transmission > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,871,992 B2 - Document ID: US10871992B2 - Status: Granted - Kind: B2 - Application number: 16/424,690 - Filed: 2019-05-29 - Published: 2019-12-05 - Granted: 2020-12-22 - Earliest claimed: 2018-05-30 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Thomas Anton Leyrer; William Cronin Wallace; David Alston Lide - Web page: https://patentgrep.com/patent/US10871992B2 ## CPC - G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues} - G06F 1/06: Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} - G06F 9/448: Execution paradigms, e.g. implementations of programming paradigms - G06F 9/5011: {the resources being hardware resources other than CPUs, Servers and Terminals} - G06F 9/5016: {the resource being the memory} - G06F 9/5038: {considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration (scheduling strategies G06F9/4881 and subgroups)} - G06F 9/52: Program synchronisation; Mutual exclusion, e.g. by means of semaphores - G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)} - G06F 13/20: for access to input/output bus - G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) - G06F 13/4068: {Electrical coupling} - G06F 16/9035: Filtering based on additional data, e.g. user or group profiles - H04L 1/0041: {Arrangements at the transmitter end} - H04L 1/0061: {Error detection codes} - G06F 2209/5012: Processor sets - G06F 2209/503: Resource availability - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A hardware state machine connected to a processor, the hardware state machine configured to receive operational codes from the processor; a multiplexer connected to the processor, the hardware state machine and a checksum circuit, the multiplexer configured to receive data from the processor; and a transmit circuit connected to the multiplexer, the transmit circuit configured to receive data from the multiplexer for transmission to a far end device, wherein the hardware state machine is further configured to, responsive receiving one or more operational codes from the processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit. ## Claims ### Claim 1 An interface circuit comprising: a state machine connected to a processor, the state machine configured to receive operational codes from the processor; a multiplexer connected to the processor, the state machine and a checksum circuit, the multiplexer configured to receive data from the processor; and a transmit circuit connected to the multiplexer, the transmit circuit configured to receive data from the multiplexer for transmission to a far end device, wherein the state machine is further configured to, responsive receiving one or more operational codes from the processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit. ### Claim 2 (depends on 1) The interface circuit of claim 1, wherein the transmit circuit is further configured to transmit a third packet while the multiplexer is receiving a fourth data packet. ### Claim 3 (depends on 2) The interface circuit of claim 2, wherein the state machine is further configured to add a virtual local area tag to the fourth data packet. ### Claim 4 (depends on 2) The interface circuit of claim 2, wherein the state machine is further configured to remove a virtual local area tag from the fourth data packet. ### Claim 5 (depends on 2) The interface circuit of claim 2, wherein the state machine is further configured to add preamble information to the fourth data packet. ### Claim 6 (depends on 1) The interface circuit of claim 1, wherein the state machine is further configured to add a sequence number to the first data packet. ### Claim 7 (depends on 1) The interface circuit of claim 1, wherein the state machine is further configured to notify the processor when a predetermined amount of memory is available in the transmit circuit. ### Claim 8 A data packet transmission method, comprising: receiving, at a multiplexer, first data from a processor; receiving, from the multiplexer, second data at a transmit circuit for transmission to a far end device, the second data based on the first data; initiating, using the transmit circuit, transmission to the far end device of a first data packet, the first data packet based on the second data; receiving, at a state machine, one or more operational codes from the processor; causing, using the state machine, a checksum circuit to alter a checksum value of the first data packet being transmitted by the transmit circuit; and causing, using the state machine, the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit. ### Claim 9 (depends on 8) The data packet transmission method of claim 8, further comprising transmitting, using the transmit circuit, a third packet while the multiplexer is receiving a fourth data packet. ### Claim 10 (depends on 9) The data packet transmission method of claim 9, further comprising adding, using the state machine, a virtual local area tag to the fourth data packet. ### Claim 11 (depends on 9) The data packet transmission method of claim 9, further comprising removing, using the state machine, a virtual local area tag from the fourth data packet. ### Claim 12 (depends on 9) The data packet transmission method of claim 9, further comprising adding, using the state machine, a preamble to the fourth data packet. ### Claim 13 (depends on 8) The data packet transmission method of claim 8, further comprising adding, using the state machine, a sequence number to the first data packet. ### Claim 14 (depends on 8) The data packet transmission method of claim 8, further comprising notifying the processor, by the state machine, when a predetermined amount of memory is available in the transmit circuit. ### Claim 15 A system on a chip, comprising: a programmable real-time processor; a state machine connected to the programmable real-time processor through a broadside interface, wherein the state machine is configured to receive operational codes from the programmable real-time processor; a checksum circuit; a multiplexer connected to the programmable real-time processor, the state machine and the checksum circuit, wherein the multiplexer is configured to receive first data from the programmable real-time processor; and a transmit circuit connected to the multiplexer, wherein the transmit circuit configured to receive second data from the multiplexer for transmission to a far end device, wherein the second data is based on the first data, wherein the state machine is further configured to, responsive receiving one or more operational codes from the programmable real-time processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit. ### Claim 16 (depends on 15) The system on a chip of claim 15, wherein the transmit circuit is further configured to transmit a third packet while the multiplexer is receiving a fourth data packet. ### Claim 17 (depends on 16) The system on a chip of claim 16, wherein the state machine is further configured to add a virtual local area tag to the fourth data packet. ### Claim 18 (depends on 16) The system on a chip of claim 16, wherein the state machine is further configured to remove a virtual local area tag from the fourth data packet. ### Claim 19 (depends on 16) The system on a chip of claim 16, wherein the state machine is further configured to add preamble data to the fourth data packet. ### Claim 20 (depends on 15) The system on a chip of claim 15, wherein the state machine is further configured to add a sequence number to the first data packet. ### Claim 21 (depends on 15) The system on a chip of claim 15, wherein the state machine is further configured to notify the programmable real-time processor when a predetermined amount of memory is available in the transmit circuit.