# US 10,871,970 B1 · Memory channel storage device detection > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,871,970 B1 - Document ID: US10871970B1 - Status: Granted - Kind: B1 - Application number: 16/235,320 - Filed: 2018-12-28 - Granted: 2020-12-22 - Earliest claimed: 2015-10-22 - Assignees: American Megatrends International, LLC - Applicants: American Megatrends International, LLC - Inventors: Senthamizhsey Subramanian; Bejean David Mosher - Web page: https://patentgrep.com/patent/US10871970B1 ## CPC - G06F 3/0626: {Reducing size or complexity of storage systems} - G06F 3/0632: {by initialisation or re-initialisation of storage systems} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 9/4403: {Processor initialisation} - G06F 9/4411: {Configuring for operating with peripheral devices; Loading of device drivers} - G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory} - G11C 29/08: Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing - G06F 2212/1056: Simplification - G06F 2212/214: Solid state disk - G06F 2212/7209: Validity control, e.g. using flags, time stamps or sequence numbers - G11C 29/10: Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns - G11C 2029/3602: {Pattern generator} - G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Technologies are disclosed herein that allow for utilization of memory channel storage (“MCS”) devices in a computing system. The MCS device may be detected during a boot phase of the computing system, and the address data for the MCS device may be detected through repeated manipulation of a logical offset. The address data may then be stored for later use in memory allocation. ## Claims ### Claim 1 A computer-implemented method, comprising: polling a serial presence detect (SPD) chipset in a memory channel storage (MCS) device to determine that the MCS device is deployed at a computer; locating an address range for the MCS device based on a logical offset from a physical memory boundary of a memory of the computer; determining a serial number for the MCS device based on the logical offset from the physical memory boundary; correlating the serial number with another serial number stored on the SPD chipset by correlating the address range with a physical slot of the computer; and storing the address range as a portion of address data for the MCS device in a non-volatile random-access memory (NVRAM) of the computer. ### Claim 2 (depends on 1) The computer-implemented method of claim 1, further comprising, reserving the address range for the MCS device in response to a next boot of the computer using the address data stored in the NVRAM. ### Claim 3 (depends on 1) The computer-implemented method of claim 1, wherein the address data is stored in the NVRAM as a data structure comprising a central processing unit (CPU) identification, a memory channel identification, a physical slot identification for the physical slot, and a base address for the MCS device. ### Claim 4 A computer-readable non-transitory storage medium having computer-executable instructions stored thereon that, in response to execution, cause a computer to: poll a serial presence detect (SPD) chipset in a memory channel storage (MCS) device to determine that the MCS device is deployed at the computer; locate an address range for the MCS device based on a logical offset from a physical memory boundary of a memory of the computer; determine a serial number for the MCS device based on the logical offset from the physical memory boundary; correlate the serial number with another serial number stored on the SPD chipset by correlating the address range with a physical slot of the computer; and store the address range as a portion of address data for the MCS device in a non-volatile random-access memory (NVRAM) of the computer. ### Claim 5 (depends on 4) The computer-readable storage medium of claim 4, having further computer-executable instructions stored thereon that, in response to execution, cause the computer to, reserve the address range for the MCS device upon a next boot of the computer using the address data stored in the NVRAM. ### Claim 6 (depends on 4) The computer-readable non-transitory storage medium of claim 4, wherein the address data is stored in the NVRAM as a data structure comprising a central processing unit (CPU) identification, a memory channel identification, a physical slot identification for the physical slot, and a base address for the MCS device. ### Claim 7 A computing system, comprising: at least one memory device having computer-executable instructions stored therein; and at least one processor functionally coupled to the at least one memory device and configured to execute the computer-readable instructions at least to, poll a serial presence detect (SPD) chipset in a memory channel storage (MCS) device to determine that the MCS device is deployed at the computing system; locate an address range for the MCS device based on a logical offset from a physical memory boundary of a memory of the computing device; determine a serial number for the MCS device based on the logical offset from the physical memory boundary; correlate the serial number with another serial number stored on the SPD chipset by correlating the address range with a physical slot of the computer; and store the address range as a portion of address data for the MCS device in a non-volatile random-access memory (NVRAM) of the computer. ### Claim 8 (depends on 7) The computing system of claim 7, wherein the at least one processor is further configured to execute the computer-executable instructions to, reserve the address range for the MCS device upon a next boot of the computing device using the address data stored in the NVRAM. ### Claim 9 (depends on 7) The computing system of claim 7, wherein the address data is stored in the NVRAM as a data structure comprising a central processing unit (CPU) identification, a memory channel identification, a physical slot identification for the physical slot, and a base address for the MCS device.