# US 10,871,967 B2 · Register read/write ordering

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- Number: US 10,871,967 B2
- Document ID: US10871967B2
- Status: Granted
- Kind: B2
- Application number: 15/012,662
- Filed: 2016-02-01
- Published: 2017-03-23
- Granted: 2020-12-22
- Earliest claimed: 2015-09-19
- Assignees: Microsoft Technology Licensing, LLC
- Applicants: Microsoft Technology Licensing, LLC
- Inventors: Douglas C. Burger; Aaron L. Smith
- Web page: https://patentgrep.com/patent/US10871967B2

## CPC

- G06F 9/3016: {Decoding the operand specifier, e.g. specifier format}
- G06F 9/268: {Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs}
- G06F 9/30007: {to perform operations on data operands}
- G06F 9/30021: {Compare instructions, e.g. Greater-Than, Equal-To, MINMAX}
- G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}
- G06F 9/30038: {using a mask}
- G06F 9/3004: {to perform operations on memory}
- G06F 9/30043: {LOAD or STORE instructions; Clear instruction}
- G06F 9/30047: {Prefetch instructions; cache control instructions}
- G06F 9/3005: {to perform operations for flow control}
- G06F 9/30058: {Conditional branch instructions}
- G06F 9/30072: {to perform conditional operations, e.g. using predicates or guards}
- G06F 9/30076: {to perform miscellaneous control operations, e.g. NOP}
- G06F 9/30087: {Synchronisation or serialisation instructions}
- G06F 9/3009: {Thread control instructions}
- G06F 9/30098: {Register arrangements}
- G06F 9/30101: {Special purpose registers}
- G06F 9/30105: {Register structure}
- G06F 9/30138: {Extension of register space, e.g. register cache}
- G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields}
- G06F 9/30167: {of immediate specifier, e.g. constants}
- G06F 9/30189: {according to execution mode, e.g. mode flag}
- G06F 9/32: Address formation of the next instruction, e.g. by incrementing the instruction counter (G06F9/38 takes precedence)
- G06F 9/323: {for indirect branch instructions}
- G06F 9/345: of multiple operands or results {(addressing multiple banks G06F12/06)}
- G06F 9/35: Indirect addressing
- G06F 9/3802: {Instruction prefetching}
- G06F 9/3804: {for branches, e.g. hedging, branch folding}
- G06F 9/3822: {Parallel decoding, e.g. parallel decode units}
- G06F 9/3824: {Operand accessing}
- G06F 9/3828: {with global bypass, e.g. between pipelines, between clusters}
- G06F 9/383: {Operand prefetching (cache prefetching G06F12/0862)}
- G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution}
- G06F 9/3838: {Dependency mechanisms, e.g. register scoreboarding}
- G06F 9/3842: {Speculative instruction execution}
- G06F 9/3848: {using hybrid branch prediction, e.g. selection between prediction techniques}
- G06F 9/3851: {from multiple instruction streams, e.g. multistreaming}
- G06F 9/3853: {of compound instructions}
- G06F 9/3854: {Instruction completion, e.g. retiring, committing or graduating}
- G06F 9/3856: {Reordering of instructions, e.g. using queues or age tags}
- G06F 9/3858: {Result writeback, i.e. updating the architectural state or memory}
- G06F 9/38585: {with result invalidation, e.g. nullification}
- G06F 9/3867: {using instruction pipelines}
- G06F 9/3888: {controlled by a single instruction for multiple threads [SIMT] in parallel}
- G06F 9/3891: {organised in groups of units sharing resources, e.g. clusters}
- G06F 9/466: {Transaction processing}
- G06F 9/528: {by using speculative mechanisms}
- G06F 11/36: Prevention of errors by analysis, debugging or testing of software
- G06F 11/3648: {using additional hardware}
- G06F 11/3656: {using a specific debug interface}
- G06F 12/0806: Multiuser, multiprocessor or multiprocessing cache systems
- G06F 12/0862: with prefetch
- G06F 12/1009: using page tables, e.g. page table structures
- G06F 13/4221: {being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus}
- G06F 15/7867: {with reconfigurable architecture}
- G06F 15/80: comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15})
- G06F 15/8007: {single instruction multiple data [SIMD] multiprocessors}
- G06F 9/3013: {according to data content, e.g. floating-point registers, address registers}
- G06F 9/321: {Program or instruction counter, e.g. incrementing}
- G06F 9/355: Indexed addressing
- G06F 9/3557: {using program counter as base address}
- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 2212/452: Instruction code
- G06F 2212/602: Details relating to cache prefetching
- G06F 2212/604: Details relating to cache allocation
- G06F 2212/62: Details of cache specific to multiprocessor cache arrangements
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Apparatus and methods are disclosed for controlling execution of register access instructions in a block-based processor architecture using a hardware structure that indicates a relative ordering of register access instruction in an instruction block. In one example of the disclosed technology, a method of operating a processor includes selecting a register access instruction of the plurality of instructions to execute based at least in part on dependencies encoded within a previous block of instructions and on stored data indicating which of the register write instructions have executed for the previous block, and executing the selected instruction. In some examples, one or more of a write mask, a read mask, a register write vector register, or a counter are used to determine register read/write dependences. Based on the encoded dependencies and the masked write vector, the next instruction block can issue when its register dependencies are available.

## Claims

### Claim 1

An apparatus comprising a processor comprising one or more processor cores, each of the cores being configurable to execute one or more instructions, each of the cores comprising:
an execution unit configured to execute register read and write instructions to read from and/or write to, respectively, a register file comprising a plurality of registers;
a hardware structure storing data including:
a register write mask storing data that indicates which registers of the register file a current group of instructions will write to, and
a register read mask storing data that indicates which registers of the register file a next group of instructions will read; and
a control unit configured to control issuing of individual register read and write instructions of the next group of instructions to the execution unit by comparing the register write mask data to the register read mask data and allowing execution of a respective one of the individual register read and write instructions when the register write mask indicates any register the respective individual instruction is dependent on has been written by the current group of instructions.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the hardware structure further comprises at least one of the following: a register write mask, a register write vector register, a content addressable memory (CAM), or a lookup table.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the data stored in the hardware structure indicates which of the registers will be written to by the core executing at least one of the instructions of the instruction block.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the data stored in the hardware structure indicates which of the registers have been written by the core during an instance of executing at least one of the instructions of the instruction block.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the data stored in the hardware structure is generated by an instruction decoder that decodes the register read and write instructions.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the data stored in the hardware structure is generated by reading write mask data from an instruction header encoded in the instruction block.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the write instructions comprise explicit register write instructions.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the control unit is further configured to compare write vector register data with write mask data from the hardware structure to determine which of the register write instructions have executed.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the control unit is further configured to compare write vector register data with write mask data from the hardware structure to determine that all register write instructions for an instruction block ordered to execute before a next instruction block will execute, and, based on the determination, issue one or more instructions of the instruction block to the execution unit.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the control unit is configured to, based on the comparing, control issuing of individual register read and write instructions.

### Claim 11

An apparatus comprising a processor comprising one or more processor cores, each of the cores being configurable to execute one or more groups of instructions, each of the cores comprising:
an execution unit configured to execute register read and write instructions contained in a group of instructions to read from and/or write to, respectively, a register file comprising a plurality of registers;
a hardware structure storing data indicative of a relative execution ordering of register read and write instructions within the group of instructions; and
a control unit configured to control issuing of register read and write instructions to the execution unit based at least in a part on the hardware structure data, the control unit comprising a counter that is incremented when a register write instruction for a previous group of instructions is executed, and wherein the control unit indicates the group of instructions is ready to execute when the counter reaches a predetermined value for a number of register writes executed in the previous group of instructions.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein the data stored in the hardware structure is generated by an instruction decoder that decodes the register read and write instructions.

### Claim 13 (depends on 11)

The apparatus of claim 11, wherein the control unit is further configured to compare write vector register data with write mask data from the hardware structure to determine that all register write instructions for an instruction block ordered to execute before a next instruction block will execute, and, based on the determination, issue one or more instructions of the instruction block to the execution unit.

### Claim 14

A method of operating a processor to execute a current block of instructions comprising a plurality of register access instructions, the method comprising:
selecting a register access instruction of the plurality of register access instructions to execute by comparing register write data for a previous block of instructions to a counter that indicates execution status of register access instructions for the current block of instructions; and
executing the selected register access instruction.

### Claim 15 (depends on 14)

The method of claim 14, wherein the stored data is stored in a write vector register, and wherein the selecting comprises comparing data from a register write mask encoded in a header of the previous block of instructions to the write vector register data.

### Claim 16 (depends on 14)

The method of claim 14, wherein:
the stored data is stored in a write vector register; and
the selecting comprises evaluating conditions for one or more predicates in the previous block of instructions and, based on the evaluating, nullifying one or more entries in the write vector registers.

### Claim 17 (depends on 14)

The method of claim 14, wherein the stored data is stored in a write vector register, the method further comprising:
comparing the write vector register data to a read mask for the block of instructions, a write mask indicating which instructions of the previous block of instructions have executed; and
based on the comparing, stalling execution of a next instruction block by processor.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
based on the comparing, performing one of the following operations: stalling execution of one or more register read instructions in the current instruction block, stalling execution of the current instruction block, initiating execution of a next instruction block, or initiating an exception handler to indicate a register access fault, flushing an instruction block, or waiting for a previous instruction block to begin decoding.

### Claim 19 (depends on 14)

The method of claim 14, wherein the stored data is stored in a write vector register, the method further comprising:
executing a register write instruction of the previous block of instructions, the register write instruction being encoded with an identifier of the register being written to; and
based on the stored data in the write vector register, executing a register read instruction in the current instruction block.

### Claim 20 (depends on 14)

One or more computer readable storage media storing computer-readable instructions that when executed by a block-based processor, cause the processor to perform the method of claim 14.