# US 10,871,966 B2 · Intelligent thread dispatch and vectorization of atomic operations

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- Number: US 10,871,966 B2
- Document ID: US10871966B2
- Status: Granted
- Kind: B2
- Application number: 16/444,188
- Filed: 2019-06-18
- Published: 2020-01-16
- Granted: 2020-12-22
- Earliest claimed: 2017-04-28
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Feng Chen; Narayan Srinivasa; Abhishek R. Appu; Altug Koker; Kamal Sinha; Balaji Vembu; Joydeep Ray; Nicolas C. Galoppo Von Borries; Prasoonkumar Surti; Ben J. Ashbaugh; Sanjeev Jahagirdar; Vasanth Ranganathan
- Web page: https://patentgrep.com/patent/US10871966B2

## CPC

- G06F 9/3009: {Thread control instructions}
- G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}
- G06F 9/30038: {using a mask}
- G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields}
- G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution}
- G06F 9/3867: {using instruction pipelines}
- G06F 9/3887: {controlled by a single instruction for multiple data lanes [SIMD]}
- G06F 9/3888: {controlled by a single instruction for multiple threads [SIMT] in parallel}
- G06F 9/38885: {Divergence aspects}
- G06F 9/5033: {considering data affinity}
- G06F 9/5066: {Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs (mappping at compile time, see G06F8/451)}
- G06F 12/0862: with prefetch
- G06N 3/044: Recurrent networks, e.g. Hopfield networks
- G06N 3/0442: characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU]
- G06N 3/045: Combinations of networks
- G06N 3/0464: Convolutional networks [CNN, ConvNet]
- G06N 3/048: Activation functions
- G06N 3/063: using electronic means
- G06N 3/084: Backpropagation, e.g. using gradient descent
- G06N 3/0895: Weakly supervised learning, e.g. semi-supervised or self-supervised learning
- G06N 3/09: Supervised learning
- G06N 3/098: Distributed learning, e.g. federated learning
- G06F 2212/602: Details relating to cache prefetching
- G06F 2212/6028: Prefetching based on hints or prefetch instructions
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A mechanism is described for facilitating intelligent dispatching and vectorizing at autonomous machines. A method of embodiments, as described herein, includes detecting a plurality of threads corresponding to a plurality of workloads associated with tasks relating to a graphics processor. The method may further include determining a first set of threads of the plurality of threads that are similar to each other or have adjacent surfaces, and physically clustering the first set of threads close together using a first set of adjacent compute blocks.

## Claims

### Claim 1

An apparatus comprising:
one or more processors including a graphics processor; and
a memory for storage of cache data for threads to be processed by the one or more processors;
wherein the one or more processors are to:
schedule a plurality of threads corresponding to a plurality of workloads for the one or more processors,
generate information regarding a data block to be processed by the plurality of threads, the information including addresses for the data block,
store the addresses as metadata in a header for the plurality of threads,
commence loading the plurality of threads for processing,
parse the metadata in the header for the plurality of threads to obtain the addresses for the data block,
prefetch data that is pointed to by the addresses obtained for the data block for one or more threads of the plurality of threads during loading of the one or more threads by the one or more processors, and
store the prefetched data for the one or more threads in the memory.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the prefetched data includes one or more values that are currently constant as the one or more threads are loaded.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the one or more threads are to be loaded into one or more shader cores.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the one or more threads are loaded in a streaming multiprocessor (SM) of a plurality of SMs of the graphics processor.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the memory is a register file.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the memory is a shared local memory.

### Claim 7

A computing system comprising:
one or more processors including a graphics processor, the graphics processor including a plurality of streaming multiprocessors; and
a shared local memory for storage of cache data for a thread group including a plurality of threads to be processed by the plurality of streaming multiprocessors;
wherein the one or more processors are to:
schedule the thread group for the plurality of streaming multiprocessors,
generate information regarding a data block to be processed by the thread group, the information including addresses for the data block,
store the addresses as metadata in a header for the plurality of threads,
commence loading the threads of the thread group for processing,
parse the metadata in the header for the thread group to obtain the addresses for the data block,
prefetch data that is pointed to by the addresses obtained for the data block for the thread group during loading of the thread group by the one or more processors, and
store the prefetched data for the thread group in the shared local memory.

### Claim 8 (depends on 7)

The computing system of claim 7, wherein the prefetched data includes one or more values that are currently constant as the threads of the thread group are loaded.

### Claim 9 (depends on 7)

The computing system of claim 7, wherein the threads of the thread group are to be loaded into one or more shader cores.

### Claim 10

At least one non-transitory machine-readable medium comprising instructions that when executed by a computing device, cause the computing device to perform operations comprising:
schedule a plurality of threads corresponding to a plurality of workloads for one or more processors including a graphics processor;
generate information regarding a data block to be processed by the plurality of threads, the information including addresses for the data block;
store the addresses as metadata in a header for the plurality of threads;
commence loading the plurality of threads for processing;
parse the metadata in the header for the plurality of threads to obtain the addresses for the data block;
prefetch data that is pointed to by the addresses obtained for the data block for one or more threads of the plurality of threads during loading of the one or more threads by the one or more processors; and
store the prefetched data for the one or more threads in a memory.

### Claim 11 (depends on 10)

The medium of claim 10, wherein the prefetched data includes one or more values that are currently constant as the one or more threads are loaded.

### Claim 12 (depends on 10)

The medium of claim 10, wherein the one or more threads are to be loaded into one or more shader cores.

### Claim 13 (depends on 10)

The medium of claim 10, wherein the one or more threads are loaded in a streaming multiprocessor (SM) of a plurality of SMs of the graphics processor.