# US 10,871,965 B2 · System and method to control the number of active vector lanes in a processor

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,871,965 B2
- Document ID: US10871965B2
- Status: Granted
- Kind: B2
- Application number: 16/236,936
- Filed: 2018-12-31
- Published: 2019-05-09
- Granted: 2020-12-22
- Earliest claimed: 2013-07-09
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Timothy David Anderson; Duc Quang Bui
- Web page: https://patentgrep.com/patent/US10871965B2

## CPC

- G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}
- G06F 1/3206: Monitoring of events, devices or parameters that trigger a change in power modality
- G06F 1/3287: by switching off individual functional units in the computer system
- G06F 9/30014: {with variable precision}
- G06F 9/30018: {Bit or string instructions}
- G06F 9/30038: {using a mask}
- G06F 9/30072: {to perform conditional operations, e.g. using predicates or guards}
- G06F 9/30109: {having multiple operands in a single register}
- G06F 9/30112: {comprising data of variable length}
- G06F 9/3013: {according to data content, e.g. floating-point registers, address registers}
- G06F 9/3887: {controlled by a single instruction for multiple data lanes [SIMD]}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

In one disclosed embodiment, a processor includes a first execution unit and a second execution unit, a register file, and a data path including a plurality of lanes. The data path and the register file are arranged so that writing to the register file by the first execution unit and by the second execution unit is allowed over the data path, reading from the register file by the first execution unit is allowed over the data path, and reading from the register file by the second execution unit is not allowed over the data path. The processor also includes a power control circuit configured to, when a transfer of data between the register file and either of the first and second execution units uses less than all of the lanes, power down the lanes of the data path not used for the transfer of the data.

## Claims

### Claim 1

A data processing system comprising:
a plurality of execution units that include at least a first execution unit and a second execution unit;
a register file;
a data path including a plurality of lanes and coupling the register file to each of the first and second execution units, wherein the data path and the register file are arranged so that writing to the register file by the first execution unit and by the second execution unit is allowed over the data path, reading from the register file by the first execution unit is allowed over the data path, and reading from the register file by the second execution unit is not allowed over the data path; and
a power control circuit configured to, when a transfer of data between the register file and either of the first execution unit and the second execution unit uses less than all of the lanes of the data path, power down the lanes of the data path not used for the transfer of the data.

### Claim 2 (depends on 1)

The data processing system of claim 1, comprising a control register to store control data that indicates which of the plurality of lanes are to be used for the transfer of the data.

### Claim 3 (depends on 2)

The data processing system of claim 2, wherein the control data is stored in a predetermined bit field within the control register.

### Claim 4 (depends on 1)

The data processing system of claim 1, wherein the data path is an n-bit wide data path, the plurality of lanes includes m lanes, and m is an integer greater than or equal to 2.

### Claim 5 (depends on 4)

The data processing system of claim 4, wherein each of the m lines is a k-bit wide lane, wherein k=n/m.

### Claim 6 (depends on 4)

The data processing system of claim 4, wherein the m lanes include a first lane having a size of x bits and a second lane having a size of y bits, wherein x and y are unequal integers.

### Claim 7 (depends on 6)

The data processing system of claim 6, wherein y is greater than x.

### Claim 8 (depends on 7)

The data processing system of claim 7, wherein y is equal to at least two times x.

### Claim 9 (depends on 7)

The data processing system of claim 7, wherein y is a multiple of x.

### Claim 10 (depends on 6)

The data processing system of claim 6, wherein the m lanes include only the first lane and the second lane, and wherein x+y=n.

### Claim 11 (depends on 6)

The data processing system of claim 6, wherein the m lanes include, in addition to the first lane and the second lane, at least a third lane, wherein n<x+y, and the third lane has a size equal to n (x+y) or less.

### Claim 12 (depends on 6)

The data processing system of claim 6, wherein:
the x-bit wide first lane is configured so that no portion of the x-bit wide first lane can be powered on without powering on the entire x-bit wide first lane or powered off without powering off the entire x-bit wide first lane; and
the y-bit wide second lane is configured so that no portion of the y-bit wide second lane can be powered on without powering on the entire y-bit wide second lane or powered off without powering off the entire y-bit wide second lane.

### Claim 13 (depends on 4)

The data processing system of claim 4, comprising a vector processor configured to execute vector instructions and scalar instructions, wherein the n-bit wide data path is a vector data path of the vector processor.

### Claim 14 (depends on 13)

The data processing system of claim 13, wherein the transfer of the data over the n-bit wide data path is in response to execution by the first execution unit of an instruction that includes a read operation, and the transfer of the data over the n-bit wide data path is the transfer of data from a register of the register file to the first execution unit.

### Claim 15 (depends on 13)

The data processing system of claim 13, wherein the transfer of the data over the n-bit wide data path is in response to execution by the first execution unit of an instruction that includes a write operation, and the transfer of the data over the n-bit wide data path is the transfer of data from the first execution unit to a register of the register file.

### Claim 16 (depends on 13)

The data processing system of claim 13, wherein:
the first execution unit is an arithmetic unit of the vector processor;
the second execution unit is one of a multiply unit or a correlation unit of the vector processor; and
the register file is a local register file of the vector processor shared by the first execution unit and another arithmetic unit of the vector processor.

### Claim 17 (depends on 13)

The data processing system of claim 13, wherein:
the first execution unit is one of a multiply unit or a correlation unit of the vector processor;
the second execution unit is an arithmetic unit of the vector processor; and
the register file is a local register file of the vector processor shared by the multiply unit and the correlation unit of the vector processor.

### Claim 18

An integrated circuit comprising:
a data processor that includes:
a plurality of execution units that include at least a first execution unit and a second execution unit;
a register file;
a data path including a plurality of lanes and coupling the register file to each of the first and second execution units, wherein the data path and the register file are arranged so that writing to the register file by the first execution unit and by the second execution unit is allowed over the data path, reading from the register file by the first execution unit is allowed over the data path, and reading from the register file by the second execution unit is not allowed over the data path; and
a power control circuit configured to, when a transfer of data between the register file and either of the first execution unit and the second execution unit uses less than all of the lanes of the data path, power down the lanes of the data path not used for the transfer of the data.

### Claim 19 (depends on 18)

The integrated circuit of claim 18, wherein the data processor is a digital signal processor.

### Claim 20 (depends on 18)

The integrated circuit of claim 18, wherein the integrated circuit is a system on chip (SoC).