# US 10,871,916 B2 · Memory controller and method of operating the same

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- Number: US 10,871,916 B2
- Document ID: US10871916B2
- Status: Granted
- Kind: B2
- Application number: 16/207,375
- Filed: 2018-12-03
- Published: 2019-10-31
- Granted: 2020-12-22
- Earliest claimed: 2018-04-30
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Young Kyun Shin
- Web page: https://patentgrep.com/patent/US10871916B2

## CPC

- G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices}
- G11C 16/10: Programming or data input circuits
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0616: {in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G11C 5/148: {Details of power up or power down circuits, standby circuits or recovery circuits}
- G11C 7/14: Dummy cell management; Sense reference voltage generators
- G11C 16/32: Timing circuits
- G11C 16/349: {Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles}
- G11C 16/3495: {Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Provided herein may be a memory controller and a method of operating the same. The memory controller may control a memory device in response to a command received from a host. The memory controller may include a write amplification factor (WAF) storage and a standby state controller. The WAF storage may store a WAF of the memory device. The standby state controller may control entry of the memory controller into a standby state based on a value of the WAF stored in the WAF storage.

## Claims

### Claim 1

A memory controller for controlling a memory device in response to a command received from a host, the memory controller comprising:
a write amplification factor (WAF) storage configured to store a WAF of the memory device; and
a standby state controller configured to control entry of the memory controller into a standby state based on a value of the WAF stored in the WAF storage.

### Claim 2 (depends on 1)

The memory controller according to claim 1, wherein the standby state controller compares the value of the WAF with a standby-prevention threshold value, and controls entry of the memory controller into the standby state based on a result of the comparison.

### Claim 3 (depends on 2)

The memory controller according to claim 2, wherein the standby state controller determines an operating mode of the memory controller as any one of a normal mode and a standby-prevention mode based on the result of the comparison.

### Claim 4 (depends on 3)

The memory controller according to claim 3, wherein the standby state controller is configured to:
when the value of the WAF is greater than the standby-prevention threshold value, control the memory controller so that the memory controller operates in the standby-prevention mode, and
when the value of the WAF is less than or equal to the standby-prevention threshold value, control the memory controller so that the memory controller operates in the normal mode.

### Claim 5 (depends on 3)

The memory controller according to claim 3, wherein the memory controller enters the standby state at a lower frequency in the standby-prevention mode than that in the normal mode.

### Claim 6 (depends on 5)

The memory controller according to claim 5, wherein:
the standby state controller determines whether to enter the standby state based on a remaining power capacity of a power source for supplying power to the memory controller,
in the normal mode, the standby state controller controls the memory controller so that, when the remaining power capacity of the power source is less than a first level, the memory controller enters the standby state,
in the standby-prevention mode, the standby state controller controls the memory controller so that, when the remaining power capacity of the power source is less than a second level, the memory controller enters the standby state, and
the second level is less than the first level.

### Claim 7 (depends on 5)

The memory controller according to claim 5, wherein:
the standby state controller determines whether to enter the standby state, based on a waiting period measured from a time at which a command is last-received from the host,
in the normal mode, the standby state controller controls the memory controller so that, when the waiting period is longer than a first period, the memory controller enters the standby state,
in the standby-prevention mode, the standby state controller controls the memory controller so that, when the waiting period is longer than a second period, the memory controller enters the standby state, and
the second period is longer than the first period.

### Claim 8 (depends on 3)

The memory controller according to claim 3, wherein the memory controller is prevented from entering the standby state in the standby-prevention mode.

### Claim 9

A method of operating a memory controller, the memory controller controlling an operation of a memory system including at least one memory device, the method comprising:
determining a write amplification factor (WAF) of the memory system;
comparing a value of the WAF with a standby-prevention threshold value; and
controlling entry of the memory system into a standby state based on a result of the comparison.

### Claim 10 (depends on 9)

The method according to claim 9, wherein controlling entry of the memory system into the standby state based on the result of the comparison comprises controlling the memory system so that the memory system operates in any one of a normal mode and a standby-prevention mode based on relative magnitudes of the value of the WAF and the standby-prevention threshold value.

### Claim 11 (depends on 10)

The method according to claim 10, wherein controlling entry of the memory system into the standby state based on the result of the comparison comprises:
when the value of the WAF is greater than the standby-prevention threshold value, controlling the memory system so that the memory system operates in the standby-prevention mode, and
when the value of the WAF is less than or equal to the standby-prevention threshold value, controlling the memory system so that the memory system operates in the normal mode.

### Claim 12 (depends on 10)

The method according to claim 10, wherein the memory system enters the standby state at a lower frequency in the standby-prevention mode than that in the normal mode.

### Claim 13 (depends on 12)

The method according to claim 12, wherein controlling entry of the memory system into the standby state comprises:
in the normal mode, when a remaining power capacity of a power source for supplying power to the memory system is less than a first level, controlling the memory system to enter the standby state,
in the standby-prevention mode, when the remaining power capacity of the power source is less than a second level, controlling the memory system to enter the standby state, and
wherein the second level is less than the first level.

### Claim 14 (depends on 12)

The method according to claim 12, wherein controlling entry of the memory system into the standby state comprises:
in the normal mode, when a waiting period measured from a time at which a command is last-received from the host is longer than a first period, controlling the memory system to enter the standby state,
in the standby-prevention mode, when the waiting period is longer than a second period, controlling the memory system to enter the standby state, and
wherein the second period is longer than the first period.

### Claim 15 (depends on 12)

The method according to claim 12, wherein, in the standby-prevention mode, the memory system is prevented from entering the standby state.

### Claim 16

A memory system comprising:
a memory device; and
a memory controller configured to control the memory device,
wherein the memory controller:
detects a write amplification factor of the memory device; and
controls a frequency or number of times the memory system is permitted to transition from an operation state to a standby state based on the write amplification factor.