# US 10,871,915 B2 · Data processing system and operating method thereof

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- Number: US 10,871,915 B2
- Document ID: US10871915B2
- Status: Granted
- Kind: B2
- Application number: 16/195,540
- Filed: 2018-11-19
- Published: 2019-07-11
- Granted: 2020-12-22
- Earliest claimed: 2018-01-11
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: An Ho Choi
- Web page: https://patentgrep.com/patent/US10871915B2

## CPC

- G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices}
- G06F 3/061: {Improving I/O performance}
- G06F 3/0656: {Data buffering arrangements}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 12/08: in hierarchically structured memory systems, e.g. virtual memory systems
- G06F 2212/1024: Latency reduction
- G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A data processing system and a method of operating the same may include a host system and a memory system. The host system may include a host memory and a host controller, and the memory system may include a memory controller and a nonvolatile memory device. The memory controller may include a data attribute determination circuit and a memory selection circuit. The data attribute determination circuit may be configured to determine an attribute of write data received from the host controller. The memory selection circuit may be configured to select, based on the determined attribute of the write data, any one of the host memory and the nonvolatile memory device as a location where the write data is to be stored.

## Claims

### Claim 1

A data processing system comprising:
a host system including a host memory and a host controller; and
a memory system including a memory controller, a buffer memory and a nonvolatile memory device,
the memory controller comprising:
a data attribute determination circuit configured to determine an attribute of write data based on a size of the write data received from the host controller;
a reference provider configured to provide a first reference size and a second reference size; and
a memory selection circuit configured to select the host memory when the size of the write data is smaller than the first reference size, and to select the nonvolatile memory device or the buffer memory, by comparing the size of the write data with the second reference size, when the size of the write data is equal to or larger than the first reference size.

### Claim 2 (depends on 1)

The data processing system of claim 1,
wherein the buffer memory is configured as a static random access memory (SRAM) or a dynamic random access memory (DRAM).

### Claim 3 (depends on 1)

The data processing system of claim 1, wherein the host controller is configured to transmit a write request including the size of the write data.

### Claim 4 (depends on 1)

The data processing system of claim 1, wherein the memory controller controls the write data to be buffered in the buffer memory and then stored in the nonvolatile memory device.

### Claim 5 (depends on 4)

The data processing system of claim 4, wherein the memory controller controls, when the buffer memory is full, the write data to be stored in the nonvolatile memory device.

### Claim 6 (depends on 1)

The data processing system of claim 1, wherein the memory selection circuit is configured to:
select the buffer memory when the size of the write data is smaller than the second reference size; and
select the nonvolatile memory device when the size of the write data is equal to or larger than the second reference size.

### Claim 7 (depends on 1)

The data processing system of claim 1,
wherein the memory selection circuit is configured to select the buffer memory when the size of the write data is smaller than the second reference size, and
wherein the memory controller controls the write data to be buffered in the buffer memory and then stored in the nonvolatile memory device.

### Claim 8 (depends on 1)

The data processing system of claim 1, wherein the second reference size corresponds to a data storage capacity which the buffer memory is able to accommodate.

### Claim 9 (depends on 1)

The data processing system of claim 1, wherein the data attribute determination circuit is configured to determine the attribute based on whether the write data is sequential data.

### Claim 10 (depends on 9)

The data processing system of claim 9, wherein the memory selection circuit is configured to:
select the nonvolatile memory device when the write data is sequential data; and
select the host memory when the write data is not sequential data.

### Claim 11

A method for operating a data processing system, the method comprising:
transmitting a write request for write data to a memory controller of a memory system, by a host controller of a host system;
determining a size of the write data based on a size of the write data, by the memory controller; and
controlling the write data to be stored selectively, based on the determined size of the write data, in a host memory of the host system or a nonvolatile memory device of the memory system, by the memory controller,
wherein the controlling of the write data to be stored selectively comprises:
controlling the write data to be stored in the host memory when the size of the write data is smaller than the first reference size, and
controlling the write data to be stored in the nonvolatile memory device or the buffer memory, by comparing the size of the write data with the second reference size, when the size of the write data is equal to or larger than the first reference size.

### Claim 12 (depends on 11)

The method of claim 11, wherein the host controller is configured to transmit the write request including the size of the write data.

### Claim 13 (depends on 11)

The method of claim 11, wherein the controlling of the write data to be stored selectively further comprises:
controlling the write data to be stored in the nonvolatile memory device when the size of the write data is smaller than the first reference size and the host memory is full.