# US 10,871,909 B2 · Block management method, memory control circuit unit and apparatus using mapping tables and block recognition machine learning with block parameters as training data > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,871,909 B2 - Document ID: US10871909B2 - Status: Granted - Kind: B2 - Application number: 15/956,749 - Filed: 2018-04-19 - Published: 2019-09-12 - Granted: 2020-12-22 - Earliest claimed: 2018-03-06 - Assignees: Phison Electronics Corp. - Applicants: Phison Electronics Corp. - Inventors: Siu-Tung Lam; Ming-Yen Lee; Kuo-Lung Lee - Web page: https://patentgrep.com/patent/US10871909B2 ## CPC - G06F 3/064: {Management of blocks} - G06F 3/0616: {in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 11/1044: {with specific ECC/EDC distribution} - G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature} - G06F 11/106: {Correcting systematically all correctable errors, i.e. scrubbing} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06N 20/00: Machine learning - G11C 8/06: Address interface arrangements, e.g. address buffers - G11C 29/028: {with adaption or trimming of parameters} - G11C 29/44: Indication or identification of errors, e.g. for repair - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - G06F 2212/502: using adaptive policy - G06F 2212/7201: Logical to physical mapping or translation of blocks or pages - G06F 2212/7211: Wear leveling - G11C 29/42: using error correcting codes [ECC] or parity check - G11C 2029/0411: {Online error correction} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A block management method, a memory control circuit unit and a memory storage apparatus for managing a plurality of physical blocks are provided. The method includes writing test data to a first physical block among the plurality of physical blocks, reading the test data from the first physical block among the plurality of physical blocks to obtain a plurality of parameters corresponding to the first physical block; grouping the first physical block into a first block group or a second block group according to the plurality of parameters corresponding to the first physical block and a rule between the plurality of parameters and grouping of the plurality of physical blocks; establishing first and second block mapping tables; and mapping logical addresses of the first and second block mapping tables to the plurality of physical blocks belonging to the first and second block groups. The parameters may comprise at least one of a read busy time parameter, a storage retention parameter, and a bit error position parameter. The bit error position parameter may be obtained according to an error bits distribution in upper, center and lower physical programming units. A usage status may be determined according to the parameters, and blocks with a usage status of good may be used first to evenly use all the plurality of physical blocks. ## Claims ### Claim 1 A block management method for managing a plurality of physical blocks in a rewritable non-volatile memory module, the block management method comprising: writing test data to a first physical block among the plurality of physical blocks; reading the test data from the first physical block among the plurality of physical blocks to obtain a plurality of parameters corresponding to the first physical block; grouping the first physical block into a first block group or a second block group according to the plurality of parameters corresponding to the first physical block and a rule between the plurality of parameters and grouping of the plurality of physical blocks; establishing a first block mapping table and a second block mapping table; sorting physical blocks belonging to the first block group; mapping logical addresses of the first block mapping table to the physical blocks belonging to the first block group; sorting physical blocks belonging to the second block group; and mapping logical addresses of the second block mapping table to the physical blocks belonging to the second block group, wherein the plurality of parameters comprises a bit error position parameter that is obtained according to an error bits distribution in an upper physical programming unit, an error bits distribution in a center physical programming unit and an error bits distribution in a lower physical programming unit among test data read from each of the plurality of physical blocks, and the rule between the plurality of parameters and the grouping of the plurality of physical blocks comprises: grouping a physical block of the plurality of physical blocks into the first block group when test data read from the physical block is correctable in an error checking and correcting operation, and grouping a further physical block of the plurality of physical blocks into the second block group when further test data read from the further physical block is uncorrectable in the error checking and correcting operation and is corrected after a re-reading operation. ### Claim 2 (depends on 1) The block management method of claim 1, wherein the logical addresses of the first block mapping table are arranged in front of the logical addresses of the second block mapping table. ### Claim 3 (depends on 2) The block management method of claim 2, wherein an overwrite frequency of data stored at the logical addresses of the first block mapping table is higher than an overwrite frequency of data stored at the logical addresses of the second block mapping table. ### Claim 4 (depends on 1) The block management method of claim 1, wherein the parameters further comprise at least one of a read busy time parameter. ### Claim 5 (depends on 1) The block management method of claim 1, further comprising: grouping the first physical block into the second block group when the test data read from the first physical block is uncorrectable in an error checking and correcting operation and is corrected after a re-reading operation. ### Claim 6 (depends on 1) The block management method of claim 1, wherein sorting the physical blocks belonging to the first block group comprises: sorting the physical blocks belonging to the first block group according to the rule before mapping the logical addresses of the first block mapping table to the physical blocks belonging to the first block group. ### Claim 7 A memory storage apparatus, comprising: a connection interface unit, configured to electrically connect to a host system; a rewritable non-volatile memory module comprising a plurality of physical blocks; and a memory control circuit unit, electrically connected to the connection interface unit and the rewritable non-volatile memory module, wherein the memory control circuit unit is configured to: give a write command sequence for writing test data to a first physical block among the plurality of physical blocks; give a read command sequence for reading the test data from the first physical block among the plurality of physical blocks to obtain a plurality of parameters corresponding to the first physical block; group the first physical block into a first block group or a second block group according to the plurality of parameters corresponding to the first physical block and a rule between the plurality of parameters and grouping of the plurality of physical blocks; establish a first block mapping table and a second block mapping table; sort physical blocks belonging to the first block group; map logical addresses of the first block mapping table to the physical blocks belonging to the first block group; sort physical blocks belonging to the second block group; map logical addresses of the second block mapping table to the physical blocks belonging to the second block group, wherein the plurality of parameters comprises a bit error position parameter that is obtained according to an error bits distribution in an upper physical programming unit, an error bits distribution in a center physical programming unit and an error bits distribution in a lower physical programming unit among test data read from each of the plurality of physical blocks, and the rule between the plurality of parameters and the grouping of the plurality of physical blocks comprises: grouping a physical block of the plurality of physical blocks into the first block group when test data read from the physical block is correctable in an error checking and correcting operation, and grouping a further physical block of the plurality of physical blocks into the second block group when further test data read from the further physical block is uncorrectable in the error checking and correcting operation and is corrected after a re-reading operation. ### Claim 8 (depends on 7) The memory storage apparatus of claim 7, wherein the memory control circuit unit is configured to arrange the logical addresses of the first block mapping table in front of the logical addresses of the second block mapping table. ### Claim 9 (depends on 8) The memory storage apparatus of claim 8, wherein an overwrite frequency of data stored at the logical addresses of the first block mapping table by the memory control circuit unit is higher than an overwrite frequency of data stored at the logical addresses of the second block mapping table by the memory control circuit unit. ### Claim 10 (depends on 7) The memory storage apparatus of claim 7, wherein the parameters further comprise at least one of a read busy time parameter and a storage retention parameter. ### Claim 11 (depends on 7) The memory storage apparatus of claim 7, wherein the memory control circuit unit is configured to group the first physical block into the second block group when the test data read from the first physical block is uncorrectable in an error checking and correcting operation and is corrected after a re-reading operation. ### Claim 12 (depends on 7) The memory storage apparatus of claim 7, wherein the memory control circuit unit is further configured to sort the physical blocks belonging to the first block group according to the rule before mapping the logical addresses of the first block mapping table to the physical blocks belonging to the first block group. ### Claim 13 A memory control circuit unit, the memory control circuit unit comprising: a host interface, configured to electrically connect to a host system; a memory interface, configured to electrically connect to a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical blocks; and a memory management circuit, electrically connected to the host interface and the memory interface, wherein the memory management circuit is configured to: give a write command sequence for writing test data to a first physical block among the plurality of physical blocks; give a read command sequence for reading the test data from the first physical block among the plurality of physical blocks to obtain a plurality of parameters corresponding to the first physical block; group the first physical block into a first block group or a second block group according the plurality of parameters corresponding to the first physical block and a rule between the plurality of parameters and grouping of the plurality of physical blocks; establish a first block mapping table and a second block mapping table; sort physical blocks belonging to the first block group; map logical addresses of the first block mapping table to the physical blocks belonging to the first block group; sort physical blocks belonging to the second block group; map logical addresses of the second block mapping table to the physical blocks belonging to the second block group, wherein the plurality of parameters comprises a bit error position parameter that is obtained according to an error bits distribution in an upper physical programming unit, an error bits distribution in a center physical programming unit and an error bits distribution in a lower physical programming unit among test data read from each of the plurality of physical blocks, and the rule between the plurality of parameters and the grouping of the plurality of physical blocks comprises: grouping a physical block of the plurality of physical blocks into the first block group when test data read from the physical block is correctable in an error checking and correcting operation, and grouping a further physical block of the plurality of physical blocks into the second block group when further test data read from the further physical block is uncorrectable in the error checking and correcting operation and is corrected after a re-reading operation. ### Claim 14 (depends on 13) The memory control circuit unit of claim 13, wherein the memory management circuit is configured to arrange the logical addresses of the first block mapping table in front of the logical addresses of the second block mapping table. ### Claim 15 (depends on 14) The memory control circuit unit of claim 14, wherein an overwrite frequency of data stored at the logical addresses of the first block mapping table by the memory management circuit is higher than an overwrite frequency of data stored at the logical addresses of the second block mapping table by the memory management circuit. ### Claim 16 (depends on 13) The memory control circuit unit of claim 13, wherein the parameters further comprise at least one of a read busy time parameter and a storage retention parameter. ### Claim 17 (depends on 13) The memory control circuit unit of claim 13, wherein the memory management circuit is configured to group the first physical block into the second block group when the test data read from the first physical block is uncorrectable in an error checking and correcting operation and is corrected after a re-reading operation. ### Claim 18 (depends on 13) The memory control circuit unit of claim 13, wherein the memory management circuit is further configured to sort the physical blocks belonging to the first block group according to the rule before mapping the logical addresses of the first block mapping table to the physical blocks belonging to the first block group.