# US 10,871,907 B2 · Sequential data optimized sub-regions in storage devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,871,907 B2 - Document ID: US10871907B2 - Status: Granted - Kind: B2 - Application number: 16/237,134 - Filed: 2018-12-31 - Published: 2020-07-02 - Granted: 2020-12-22 - Earliest claimed: 2018-12-31 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: David Aaron Palmer; Sean L. Manion; Jonathan Parry; Stephen Hanna; Qing Liang; Nadav Grosz; Christian M. Gyllenskog; Kulachet Tanpairoj - Web page: https://patentgrep.com/patent/US10871907B2 ## CPC - G06F 3/0631: {by allocating resources to storage systems} - G06F 3/061: {Improving I/O performance} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 2212/1016: Performance improvement - G06F 2212/7201: Logical to physical mapping or translation of blocks or pages - G06F 2212/7204: Capacity control, e.g. partitioning, end-of-life degradation - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller. ## Claims ### Claim 1 A storage system comprising: a memory array; a random access memory configured to store at least a portion of one or more logical-to-physical (L2P) mapping tables; and a memory controller, wherein the memory controller is programmed to perform operations including: partitioning the memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges; assigning a first granularity of a first L2P mapping table entry for the first portion of the memory array designated for a first usage; assigning a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity; storing data indicative of size of the first granularity and the second granularity in the memory array; and storing at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in the random access memory. ### Claim 2 (depends on 1) The system of claim 1, wherein data indicative of size of the first and second granularity are also stored in a region table in the controller. ### Claim 3 (depends on 1) The system of claim 1, wherein the first granularity is larger than the second granularity. ### Claim 4 (depends on 1) The system of claim 1, wherein the second granularity is larger than the first granularity. ### Claim 5 (depends on 1) The system of claim 1, wherein the first portion and the second portion are different memory types. ### Claim 6 (depends on 1) The system of claim 1, wherein partitioning the memory array into a first portion and a second portion includes partitioning the memory array at startup. ### Claim 7 (depends on 1) The system of claim 1, wherein partitioning the memory array into a first portion and a second portion includes partitioning the memory array during runtime. ### Claim 8 (depends on 1) The system of claim 1, wherein partitioning the memory array into a first portion and a second portion includes partitioning the memory array at startup and re-partitioning the memory array during runtime. ### Claim 9 A method comprising: partitioning, by a memory controller, a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges; assigning, by the memory controller, a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage; assigning, by the memory controller, a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity; storing, by the memory controller, data indicative of size of the first granularity and the second granularity in the memory array; and storing, by the memory controller, at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller. ### Claim 10 (depends on 9) The method of claim 9, further comprising: partitioning, by the memory controller, the memory array to include a third portion, the first portion, second portion and third portion having non-overlapping logical block addressing (LBA) ranges; and assigning, by the memory controller, a third granularity of a third L2P mapping table entry for the third portion of the memory array designated for a third usage. ### Claim 11 (depends on 10) The method of claim 10, wherein the third granularity is not equal to the first granularity and the second granularity. ### Claim 12 (depends on 10) The method of claim 10, further comprising: storing, by the memory controller, the third granularity in the memory array; and storing, by the memory controller, at least a portion of the third L2P mapping table entry in the L2P cache of the memory controller. ### Claim 13 (depends on 10) The method of claim 10, further comprising: partitioning, by the memory controller, the memory array to include a fourth portion, the first portion, second portion, third portion and fourth portion having non-overlapping logical block addressing (LBA) ranges; and assigning, by the memory controller, a fourth granularity of a fourth L2P mapping table entry for the fourth portion of the memory array designated for a fourth usage. ### Claim 14 (depends on 13) The method of claim 13, wherein the fourth granularity is not equal to the first granularity, the second granularity and the third granularity. ### Claim 15 (depends on 13) The method of claim 13, further comprising: storing, by the memory controller, the fourth granularity in the memory array; and storing, by the memory controller, at least a portion of the fourth L2P mapping table entry in the L2P cache of the memory controller. ### Claim 16 A non-transitory computer readable medium comprising instructions thereon that, when executed by a processor, cause the processor to perform operations comprising: partitioning a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges; assigning a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage; assigning a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity; storing data indicative of size of the first granularity and the second granularity in the memory array; and storing at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache. ### Claim 17 (depends on 16) The computer readable medium of claim 16, wherein the first portion and the second portion are different memory types. ### Claim 18 (depends on 16) The computer readable medium of claim 16, wherein partitioning the memory array into a first portion and a second portion includes partitioning the memory array at startup. ### Claim 19 (depends on 16) The computer readable medium of claim 16, wherein partitioning the memory array into a first portion and a second portion includes partitioning the memory array during runtime. ### Claim 20 (depends on 16) The computer readable medium of claim 16, wherein partitioning the memory array into a first portion and a second portion includes partitioning the memory array at startup and re-partitioning the memory array during runtime.