# US 10,871,906 B2 · Periphery shoreline augmentation for integrated circuits

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- Number: US 10,871,906 B2
- Document ID: US10871906B2
- Status: Granted
- Kind: B2
- Application number: 16/147,150
- Filed: 2018-09-28
- Published: 2020-04-02
- Granted: 2020-12-22
- Earliest claimed: 2018-09-28
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Chee Hak Teh; Curtis Wortman; Jeffrey Erik Schulz
- Web page: https://patentgrep.com/patent/US10871906B2

## CPC

- G06F 3/0629: {Configuration or reconfiguration of storage systems}
- G06F 3/0617: {in relation to availability}
- G06F 3/0658: {Controller construction arrangements}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 13/385: {for adaptation of a particular data processing system to different peripheral devices}
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- H03K 19/17732: Macroblocks
- G11C 7/18: Bit line organisation; Bit line lay-out
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A multichip package may include at least a main die mounted on a substrate. The main die may be coupled to one or more transceiver dies also mounted on the substrate. The main die may include one or more universal interface blocks configured to interface with an on-package memory device or an on-package expansion die, both of which can be mounted on the substrate. The expansion die may include external memory interface (EMIF) components for communicating with off-package memory devices and/or bulk random-access memory (RAM) components for storing large amounts of data for the main die. Smaller input-output blocks such as GPIO (general purpose input-output) or LVDS (low-voltage differential signaling) interfaces may be formed within the core fabric of the main die without causing routing congestion while providing the necessary clock source.

## Claims

### Claim 1

A multichip package, comprising:
a substrate; and
an integrated circuit die mounted on the substrate, wherein the integrated circuit die has a periphery, wherein the integrated circuit die comprises a universal interface block formed along the periphery of the integrated circuit die, wherein the universal interface block is operable to communicate with at least an on-package memory die and an on-package expansion die, and wherein the on-package expansion die includes external memory interface (EMIF) components configured to communicate with memory devices external to the multichip package.

### Claim 2 (depends on 1)

The multichip package of claim 1, wherein the on-package expansion die is mounted on the substrate, and wherein the external memory interface components on the on-package expansion die are configured to support double date rate (DDR) or quad data rate (QDR) external memory interfaces.

### Claim 3 (depends on 2)

The multichip package of claim 2, wherein the on-package expansion die further includes bulk random-access memory components.

### Claim 4 (depends on 3)

The multichip package of claim 3, wherein the bulk random-access memory components comprise static random-access memory (SRAM) blocks.

### Claim 5 (depends on 3)

The multichip package of claim 3, wherein the integrated circuit die further comprises:
additional bulk random-access memory components formed along the periphery of the integrated circuit die.

### Claim 6 (depends on 2)

The multichip package of claim 2, wherein the integrated circuit die further comprises:
additional external memory interface components formed along the periphery of the integrated circuit die, wherein the additional external memory interface components are also configured to communicate with memory devices external to the multichip package.

### Claim 7 (depends on 1)

The multichip package of claim 1, wherein the interface between the on-package expansion die and the universal interface block on the integrated circuit die is implemented using an embedded multi-die interconnect bridge formed in a top surface of the substrate.

### Claim 8 (depends on 1)

The multichip package of claim 1, wherein the on-package memory die is mounted on the substrate, and wherein the on-package memory die is configured to offer higher bandwidth than the external memory interface components.

### Claim 9 (depends on 1)

The multichip package of claim 1, wherein the integrated circuit die further comprises:
core routing fabric formed within its periphery; and
general purpose input-output (GPIO) or low-voltage differential signaling (LVDS) buffers formed within the core routing fabric, wherein the GPIO and LVDS buffers are configured to provide a clock source for the core routing fabric, and wherein there is no external memory interface (EMIF) components formed within the core routing fabric.

### Claim 10 (depends on 1)

The multichip package of claim 1, further comprising:
a transceiver die coupled to a corresponding transceiver interface block on the integrated circuit die, wherein the transceiver die is configured to communicate with off-package devices at data rates exceeding 10 Gbps.

### Claim 11

Circuitry, comprising:
a package substrate;
a main die mounted on the package substrate;
a memory die mounted on the package substrate, wherein the memory die is coupled to a first universal interface block in the main die; and
an expansion die mounted on the package substrate, wherein the expansion die is coupled to a second universal interface block in the main die, wherein the first and second universal interface blocks are structurally identical, and wherein the expansion die includes external memory interface (EMIF) blocks configured to communicate with off-package memory devices that are not mounted on the package substrate.

### Claim 12 (depends on 11)

The circuitry of claim 11, further comprising:
a transceiver die mounted on the package substrate, wherein the transceiver die is configured to communicate with off-package devices at data rates exceeding 50 Gbps.

### Claim 13 (depends on 11)

The circuitry of claim 11, wherein the expansion die further comprises bulk random-access memory (RAM) blocks.

### Claim 14 (depends on 13)

The circuitry of claim 13, wherein the first and second universal interface blocks are formed at peripheral edges of the main die, and wherein the main die further comprises:
core routing fabric formed within its peripheral edges, wherein there is no external memory interface (EMIF) blocks formed through the core routing fabric.

### Claim 15 (depends on 14)

The circuitry of claim 14, wherein the main die further comprises additional external memory interface components formed along the peripheral edges of the main die or embedded static random-access memory components formed along the peripheral edges of the main die.

### Claim 16

An integrated circuit die formed within a package, comprising:
a periphery;
a transceiver interface block formed along the periphery, wherein the transceiver interface block is configured to communicate with a transceiver die formed within the same package as the integrated circuit die; and
a universal interface block formed along the periphery, wherein the universal interface block is operable to communicate with a memory die formed within the same package as the integrated circuit die and with an expansion die formed within the same package as the integrated circuit die, and wherein the integrated circuit die offloads at least some peripheral input-output components onto the expansion die.

### Claim 17 (depends on 16)

The integrated circuit die of claim 16, wherein the expansion die comprises bulk random-access memory (RAM) circuitry.

### Claim 18 (depends on 17)

The integrated circuit die of claim 17, wherein the expansion die further comprises external memory interface (EMIF) circuitry.

### Claim 19 (depends on 18)

The integrated circuit die of claim 18, wherein the interface between the universal interface block and the expansion die has a bandwidth that is partitioned between the EMIF and bulk RAM circuities using an addressable memory mapping scheme.

### Claim 20 (depends on 18)

The integrated circuit die of claim 18, wherein the interface between the universal interface block and the expansion die has a bandwidth that is partitioned between the EMIF and bulk RAM circuities using a strict channel partitioning scheme.