# US 10,871,903 B2 · Achieving consistent read times in multi-level non-volatile memory

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- Number: US 10,871,903 B2
- Document ID: US10871903B2
- Status: Granted
- Kind: B2
- Application number: 16/376,283
- Filed: 2019-04-05
- Published: 2019-10-31
- Granted: 2020-12-22
- Earliest claimed: 2016-12-30
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Anand S. Ramalingam; Pranav Kalavade
- Web page: https://patentgrep.com/patent/US10871903B2

## CPC

- G06F 3/0613: {in relation to throughput}
- G06F 3/0652: {Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket}
- G06F 3/0656: {Data buffering arrangements}
- G06F 3/0658: {Controller construction arrangements}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 12/0292: {using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10)}
- G06F 2212/1016: Performance improvement
- G06F 2212/2022: Flash memory
- G06F 2212/7204: Capacity control, e.g. partitioning, end-of-life degradation
- G06F 2212/7205: Cleaning, compaction, garbage collection, erase control
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Systems, apparatuses and methods may provide for technology that reads a lower page, one or more intermediate pages and a last page from a set of multi-level non-volatile memory (NVM) cells, wherein one or more of a lower read time associated with the lower page or a last read time associated with the last page is substantially similar to an intermediate read time associated with the one or more intermediate pages.

## Claims

### Claim 1

A system comprising:
a device controller apparatus including a transfer buffer; and
a non-volatile memory (NVM) communicatively coupled to the device controller apparatus, the NVM including:
a set of multi-level NVM cells that is to correspond to a lower page, one or more intermediate pages and a last page; and
a chip controller apparatus that includes one or more substrates and logic, implemented in fixed-functionality hardware and coupled to the one or more substrates, the logic to:
program the set of multi-level NVM cells,
read from the set of multi-level NVM cells, and
determine bit values of the lower page based on multiple comparisons between read levels to read the lower page.

### Claim 2 (depends on 1)

The system of claim 1, wherein the logic is to:
program the set of multi-level NVM cells on a page-by-page basis.

### Claim 3 (depends on 1)

The system of claim 1, wherein:
the last page is to correspond to a first bit of the set of multi-level NVM cells;
an upper page of the one or more intermediate pages is to correspond to a second bit of the set of multi-level NVM cells; and
the lower page is to correspond to a third bit of the set of multi-level NVM cells.

### Claim 4 (depends on 1)

The system of claim 1, wherein:
the last page is to correspond to a first bit of the set of multi-level NVM cells;
an extra page of the one or more intermediate pages is to correspond to a second bit of the set of multi-level NVM cells;
an upper page of the one or more intermediate pages is to correspond to a third bit of the set of multi-level NVM cells; and
the lower page is to correspond to a fourth bit of the set of multi-level NVM cells.

### Claim 5 (depends on 1)

The system of claim 1, wherein the logic is to:
conduct the multiple comparisons between the read levels.

### Claim 6 (depends on 5)

The system of claim 5, wherein the multiple comparisons are to be conducted between three read levels.

### Claim 7 (depends on 5)

The system of claim 5, wherein the multiple comparisons are to be conducted between four read levels.

### Claim 8 (depends on 1)

The system of claim 1, wherein the set of multi-level NVM cells includes one or more of a quad level cell architecture or a tri-level cell architecture.

### Claim 9 (depends on 1)

The system of claim 1, wherein the device controller apparatus is to store garbage collection data from the lower page, the one or more intermediate pages and the last page to the transfer buffer, and write the garbage collection data to different locations in the set of multi-level NVM cells.

### Claim 10

A non-volatile memory (NVM) comprising:
a set of multi-level NVM cells that is to correspond to a lower page, one or more intermediate pages and a last page; and
a chip controller apparatus that includes one or more substrates and logic, implemented in fixed-functionality hardware and coupled to the one or more substrates, the logic to:
program the set of multi-level NVM cells,
read from the set of multi-level NVM cells, and
determine bit values of the lower page based on multiple comparisons between read levels to read the lower page.

### Claim 11 (depends on 10)

The NVM of claim 10, wherein the logic is to:
program the set of multi-level NVM cells on a page-by-page basis.

### Claim 12 (depends on 10)

The NVM of claim 10, wherein:
the last page is to correspond to a first bit of the set of multi-level NVM cells;
an upper page of the one or more intermediate pages is to correspond to a second bit of the set of multi-level NVM cells; and
the lower page is to correspond to a third bit of the set of multi-level NVM cells.

### Claim 13 (depends on 10)

The NVM of claim 10, wherein:
the last page is to correspond to a first bit of the set of multi-level NVM cells;
an extra page of the one or more intermediate pages is to correspond to a second bit of the set of multi-level NVM cells;
an upper page of the one or more intermediate pages is to correspond to a third bit of the set of multi-level NVM cells; and
the lower page is to correspond to a fourth bit of the set of multi-level NVM cells.

### Claim 14 (depends on 10)

The NVM of claim 10, wherein the logic is to:
conduct the multiple comparisons between the read levels.

### Claim 15 (depends on 14)

The NVM of claim 14, wherein the multiple comparisons are to be conducted between three read levels.

### Claim 16 (depends on 14)

The NVM of claim 14, wherein the multiple comparisons are to be conducted between four read levels.

### Claim 17 (depends on 10)

The NVM of claim 10, wherein the set of multi-level NVM cells includes a quad level cell architecture.

### Claim 18 (depends on 10)

The NVM of claim 10, wherein the set of multi-level NVM cells includes a tri-level cell architecture.

### Claim 19

A method comprising:
programming, with logic implemented in fixed-functionality hardware, a set of multi-level NVM cells, wherein the set of multi-level NVM cells correspond to a lower page, one or more intermediate pages and a last page;
reading, with the logic, from the set of multi-level NVM cells; and
determining, with the logic, bit values of the lower page based on multiple comparisons between read levels to read the lower page.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
programming, with the logic, the set of multi-level NVM cells on a page-by-page basis.

### Claim 21 (depends on 19)

The method of claim 19, wherein:
the last page is to correspond to a first bit of the set of multi-level NVM cells;
an upper page of the one or more intermediate pages is to correspond to a second bit of the set of multi-level NVM cells; and
the lower page is to correspond to a third bit of the set of multi-level NVM cells.

### Claim 22 (depends on 19)

The method of claim 19, wherein:
the last page is to correspond to a first bit of the set of multi-level NVM cells;
an extra page of the one or more intermediate pages is to correspond to a second bit of the set of multi-level NVM cells;
an upper page of the one or more intermediate pages is to correspond to a third bit of the set of multi-level NVM cells; and
the lower page is to correspond to a fourth bit of the set of multi-level NVM cells.

### Claim 23 (depends on 19)

The method of claim 19, further comprising:
conducting, with the logic, the multiple comparisons between the read levels.

### Claim 24 (depends on 23)

The method of claim 23, wherein the multiple comparisons are to be conducted between three read levels.

### Claim 25 (depends on 23)

The method of claim 23, wherein the multiple comparisons are to be conducted between four read levels.