# US 10,871,811 B2 · Power chip > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,871,811 B2 - Document ID: US10871811B2 - Status: Granted - Kind: B2 - Application number: 16/159,803 - Filed: 2018-10-15 - Published: 2019-03-21 - Granted: 2020-12-22 - Earliest claimed: 2016-08-26 - Assignees: Delta Electronics (Shanghai) Co., Ltd. - Applicants: Delta Electronics (Shanghai) CO., LTD - Inventors: Yan Chen; Xiaoni Xin; Le Liang; Shouyu Hong; Jianhong Zeng - Web page: https://patentgrep.com/patent/US10871811B2 ## CPC - G06F 1/26: Power supply means, e.g. regulation thereof (for memories G11C) - H03K 17/168: {in composite switches} - H10W 20/427: {Power or ground buses} - H10W 20/496: {Capacitor integral with wiring layers} - H10W 44/20: at high-frequency [HF] or radio frequency [RF] - H10W 70/685: comprising multiple insulating layers - H10W 90/00: Package configurations - H03K 17/145: {in field-effect transistor switches} - H03K 17/162: {without feedback from the output circuit to the control circuit} - H10D 99/00: Subject matter not provided for in other groups of this subclass - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A power chip includes: a first power switch, formed in a wafer region and having a first and a second metal electrodes; a second power switch, formed in the wafer region and having a third and a fourth metal electrodes, wherein the first and second power switches respectively constitute an upper bridge arm and a lower bridge arm of a bridge circuit, and the first and second power switches are alternately arranged along a first direction; and a metal region, at least including a first metal layer, a second metal layer and a third metal layer that are stacked, each metal layer including a first to a third strip electrodes, and strip electrodes with the same voltage potential in two adjacent metal layers are electrically coupled, wherein a routing direction of the strip electrode in the first metal layer is substantially perpendicular to the first direction. ## Claims ### Claim 1 A power chip, comprising: a first power switch, formed in a wafer region, each first power switch having a first metal electrode and a second metal electrode; a second power switch, formed in the wafer region, each second power switch having a third metal electrode and a fourth metal electrode, wherein the first power switch and the second power switch respectively constitute an upper bridge arm and a lower bridge arm of a bridge circuit, at least one bridge arm of the upper bridge arm and the lower bridge arm comprises two or more power switches parallel to each other, wherein the first power switch and the second power switch are arranged alternately along a first direction; and a metal region, comprising a first metal layer, a second metal layer and a third metal layer that are stacked, wherein each of the first metal layer, the second metal layer and the third metal layer comprises first strip electrodes, second strip electrodes and third strip electrodes, and strip electrodes among the first, second and third strip electrodes with the same voltage potential in two adjacent metal layers among the first metal layer, the second metal layer and the third metal layer are electrically coupled, wherein a routing direction of at least one of the first, second and third strip electrodes in the first metal layer is substantially perpendicular to the first direction. ### Claim 2 (depends on 1) The power chip according to claim 1, wherein the first metal layer is located above the first and second power switches which are arranged alternately, the first and second strip electrodes in the first metal layer are alternately arranged in parallel in a region above the first power switch; the second and third strip electrodes in the first metal layer are alternately arranged in parallel in a region above the second power switch; and the first strip electrodes, the second strip electrodes and the third strip electrodes in the first metal layer are coupled with the first metal electrodes, the second metal electrodes and the third metal electrodes of the first or second power switches respectively. ### Claim 3 (depends on 1) The power chip according to claim 1, wherein the second metal layer is located above the first metal layer and any of the first strip electrodes in the second metal layer is coupled with all of the first strip electrodes in the first metal layer above at least one of the first power switch. ### Claim 4 (depends on 1) The power chip according to claim 1, wherein the second metal layer is located above the first metal layer and any of the third strip electrodes in the second metal layer is coupled with all of the third strip electrodes in the first metal layer above at least one of the second power switch. ### Claim 5 (depends on 1) The power chip according to claim 1, wherein the second metal layer is located above the first metal layer and any of the second strip electrodes in the second metal layer is coupled with all of the second strip electrodes in the first metal layer above at least one of the first power switch and the second power switch. ### Claim 6 (depends on 1) The power chip according to claim 1, wherein the first and second strip electrodes in the second metal layer are alternately arranged in parallel; and the second and third strip electrodes in the second metal layer are alternately arranged in parallel. ### Claim 7 (depends on 6) The power chip according to claim 6, wherein the second metal layer is located above the first metal layer and a projection of the first strip electrodes in the second metal layer falls within a surface area of the first power switch. ### Claim 8 (depends on 6) The power chip according to claim 6, wherein the second metal layer is located above the first metal layer and a projection of the third strip electrodes in the second metal layer falls within a surface area of the second power switch. ### Claim 9 (depends on 6) The power chip according to claim 6, wherein in the second metal layer an arrangement width of a region with a high current density is larger than an arrangement width of a region with a low current density in each of the first, second and third strip electrodes. ### Claim 10 (depends on 1) The power chip according to claim 1, wherein a routing direction of at least one of the first, second and third strip electrodes in the second metal layer is substantially perpendicular to the routing direction of the at least one of the first, second and third strip electrodes in the first metal layer. ### Claim 11 (depends on 1) The power chip according to claim 1, wherein the third metal layer is located above the second metal layer and any of the first strip electrodes in the third metal layer is coupled with all of the first strip electrodes in the second metal layer, any of the third strip electrodes in the third metal layer is coupled with all of the third strip electrodes in the second metal layer and any of the second strip electrodes in the third metal layer is coupled with all of the second strip electrodes in the second metal layer. ### Claim 12 (depends on 11) The power chip according to claim 11, wherein a routing direction of at least one of the first, second and third strip electrode in the third metal layer is substantially perpendicular to a routing direction of the at least one of the first, second and third strip electrodes in the second metal layer. ### Claim 13 (depends on 12) The power chip according to claim 12, wherein in the third metal layer, the first strip electrodes are arranged at one side of the second strip electrodes, and the third strip electrodes are arranged at the other side of the second strip electrodes. ### Claim 14 (depends on 11) The power chip according to claim 11, wherein the first, second and third strip electrodes in the third metal layer are arranged in parallel. ### Claim 15 (depends on 11) The power chip according to claim 11, wherein in the third metal layer an arrangement width of a region with a high current density is larger than an arrangement width of a region with a low current density in each of the first, second and third strip electrodes. ### Claim 16 (depends on 1) The power chip according to claim 1, the width of the strip electrodes having a voltage level in the first metal layer is smaller than that of the strip electrodes having the voltage level in the second metal layer and the width of the strip electrodes having the voltage level in the second metal layer is smaller than that of the strip electrodes having the voltage level in the third metal layer. ### Claim 17 A power chip, comprising: a first power switch, formed in a wafer region, each first power switch having a first metal electrode and a second metal electrode; a second power switch, formed in the wafer region, each second power switch having a third metal electrode and a fourth metal electrode, wherein the first power switch and the second power switch respectively constitute an upper bridge arm and a lower bridge arm of a bridge circuit, at least one bridge arm of the upper bridge arm and the lower bridge arm comprises two or more power switches parallel to each other, wherein the first power switch and the second power switch are arranged alternately along a first direction; and a metal region, comprising a first metal layer, a second metal layer and a third metal layer that are stacked in sequence, wherein each of the first metal layer, the second metal layer and the third metal layer comprises first strip electrodes, second strip electrodes and third strip electrodes, and strip electrodes among the first, second and third strip electrodes with the same voltage potential in two adjacent metal layers among the first metal layer, the second metal layer and the third metal layer are electrically coupled, wherein in each of the first strip electrodes, the second strip electrodes and the third strip electrodes of the second metal layer, an arrangement width of a region with a high current density is larger than an arrangement width of a region with a low current density.