# US 10,871,688 B2 · Array substrate, manufacturing method thereof, and display device

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- Number: US 10,871,688 B2
- Document ID: US10871688B2
- Status: Granted
- Kind: B2
- Application number: 15/512,582
- Filed: 2016-05-27
- Published: 2019-01-10
- Granted: 2020-12-22
- Earliest claimed: 2016-03-14
- Assignees: Boe Technology Group Co., Ltd.; Beijing Boe Display Technology Co., Ltd.
- Applicants: Boe Technology Group Co., Ltd.; Beijing Boe Display Technology Co., Ltd.
- Inventors: Jinyu Ren; Dan Wang; Changjian Xu; Guojing Ma; Bo Zhou
- Web page: https://patentgrep.com/patent/US10871688B2

## CPC

- G02F 1/136227: {Through-hole connection of the pixel electrode to the active element through an insulation layer}
- G02F 1/134309: {characterised by their geometrical arrangement}
- G02F 1/13439: {characterised by their electrical, optical, physical properties; materials therefor; method of making}
- H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D 86/0212: {comprising manufacture, treatment or coating of substrates}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- G02F 1/1337: Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- G02F 2201/121: common or background
- G02F 2201/123: pixel
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An array substrate, a manufacturing method thereof and a display device are provided. The array substrate includes a first conductive pattern, an insulation layer covering the first conductive pattern, and a second conductive pattern arranged on the insulation layer. The insulation layer includes a via-hole through which the first conductive pattern is connected to the second conductive pattern. A conductive post connected to the first conductive pattern and the second conductive pattern is formed in the via-hole.

## Claims

### Claim 1

An array substrate, comprising a base substrate, a first conductive pattern, an insulation layer covering the first conductive pattern, and a second conductive pattern arranged on the insulation layer, wherein the insulation layer comprises a via-hole through which the first conductive pattern is connected to the second conductive pattern, and the array substrate further comprises a conductive post,
the conductive post fills in the via-hole, the first conductive pattern is not in direct contact with the second conductive pattern, and the first conductive pattern is connected to the second conductive pattern through the conductive post, and
the conductive post comprises a resin column object and a conductive material enclosing the resin column object,
the insulation layer comprises a passivation layer, an upper surface of the conductive post is coplanar with an upper surface of the passivation layer and
the conductive post is in direct contact with the base substrate,
wherein the first conductive pattern is a drain electrode of a thin film transistor (TFT), and the second conductive pattern is a pixel electrode.

### Claim 2 (depends on 1)

The array substrate according to claim 1, wherein the conductive post comprises an organic conductive polymer or a metal.

### Claim 3 (depends on 1)

The array substrate according to claim 1, wherein an outer surface of the conductive post is in contact with an entire inner surface of the via-hole.

### Claim 4 (depends on 1)

The array substrate according to claim 1, wherein the pixel electrode covers the upper surface of the conductive post.

### Claim 5 (depends on 1)

A display device, comprising the array substrate according to claim 1.

### Claim 6

A method for manufacturing an array substrate, the array substrate comprising a base substrate, a first conductive pattern, an insulation layer covering the first conductive pattern, and a second conductive pattern arranged on the insulation layer, the insulation layer comprising a via-hole through which the first conductive pattern is connected to the second conductive pattern, wherein the method comprises:
forming a conductive post connected to the first conductive pattern in the via-hole before forming the second conductive pattern, and;
forming the second conductive pattern connected to the conductive post,
wherein the conductive post fills in the via-hole, the first conductive pattern is not in direct contact with the second conductive pattern, and the first conductive pattern is connected to the second conductive pattern through the conductive post, and
the conductive post comprises a resin column object and a conductive material enclosing the resin column object,
the insulation layer comprises a passivation layer, an upper surface of the conductive post is coplanar with an upper surface of the passivation layer, and
the conductive post is in direct contact with the base substrate,
wherein the first conductive pattern is a drain electrode of a thin film transistor (TFT), and the second conductive pattern is a pixel electrode.

### Claim 7 (depends on 6)

The method according to claim 6, wherein,
prior to forming the conductive post connected to the first conductive pattern in the via-hole, the method further comprises:
providing the base substrate;
forming a gate electrode of the TFT on the base substrate;
forming a gate insulation layer; and
forming a pattern of an active layer.