# US 10,871,518 B2 · Systems and methods for determining systematic defects > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,871,518 B2 - Document ID: US10871518B2 - Status: Granted - Kind: B2 - Application number: 16/129,433 - Filed: 2018-09-12 - Published: 2019-04-18 - Granted: 2020-12-22 - Earliest claimed: 2017-09-29 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Sandeep Kumar Goel; Yun-Han Lee; Ankita Patidar - Web page: https://patentgrep.com/patent/US10871518B2 ## CPC - G01R 31/318544: {Scanning methods, algorithms and patterns (G01R31/3183 takes precedence)} - G01R 31/318541: {Scan latches or cell details} - G11C 29/14: Implementation of control logic, e.g. test mode decoders - G11C 29/32: Serial access; Scan testing - G01R 31/31853: {Test of registers} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Methods and systems for determining a systematic defect in a circuit under test is provided. Elements of the circuit under test converted into scan cells. A first scan chain that includes a first plurality of scan cells is formed. Each scan cell of the first plurality of scan cells of the first scan chain are of a first cell type. The first scan chain contains a first scan input and a first scan output. A first test pattern is applied at the scan input and a first test output is collected for the applied first test pattern at the first scan output. The collected first test output is compared with a first expected test output. The first cell type is marked to be a suspect for a systematic defect when the first test output is different from the first expected test output. ## Claims ### Claim 1 A method of determining a systematic defect in a first circuit under test, the method comprising: converting elements of a circuit under test into scan cells; forming a first scan chain comprising a first plurality of scan cells selected from the scan cells converted from the elements of the circuit under test, wherein each scan cell of the first plurality of scan cells of the first scan chain are of a first cell type, and wherein the first scan chain comprises a first scan input and a first scan output; applying a first test pattern at the scan input of the first scan chain; collecting a first test output for the first test pattern at the first scan output of the first scan chain; comparing the first test output with a first expected test output for the first test pattern; and determining, when the first test output is different from the first expected test output, the first cell type to be a suspect for a systematic defect. ### Claim 2 (depends on 1) The method of claim 1, further comprising: forming a second scan chain comprising a second plurality of scan cells selected from the scan cell converted from the elements of the circuit under test, wherein each scan cell of the second plurality of scan cells of the second scan chain are of a second cell type, and wherein the second scan chain comprises a second scan input and a second scan output; applying a second test pattern at the second scan input of the second scan chain; receiving a second test output for the second test pattern at the second scan output of the second scan chain; comparing the second test output with a second expected test output for the second test pattern; and determining, when the second test output is same as the second expected test output, the second cell type not to be a suspect for the systematic defect. ### Claim 3 (depends on 1) The method of claim 1, wherein the circuit under test is obtained from a first die, and wherein the method further comprises: determining the systematic defect for the circuit under test obtained from at least one second die; and aggregating the suspect obtained for the circuit under test obtained from the at least one second die with the suspect for the circuit under test obtained from the first die. ### Claim 4 (depends on 1) The method of claim 1, further comprising splitting the first scan chain into two or more scan chains when a number of the first plurality of scan cells is more than a predetermined number. ### Claim 5 (depends on 1) The method of claim 1, wherein forming the first scan chain comprises forming the first scan chain comprising the first plurality of scan cells of the first cell type comprising a predetermined cell design. ### Claim 6 (depends on 1) The method of claim 1, wherein forming the first scan chain comprises forming the first scan chain comprising the first plurality of scan cells of the first cell type comprising a suspect scan cell design. ### Claim 7 (depends on 1) The method of claim 1, further comprising incrementally mixing at least one scan cell of a second cell type into the first scan chain. ### Claim 8 (depends on 1) The method of claim 1, further comprising: fixing the systematic defect associated with the first cell type; and determining whether a second plurality of scan cells of a second cell type contain the systematic defect. ### Claim 9 (depends on 1) The method of claim 1, further comprising: forming a second scan chain comprising a second plurality of scan cells, wherein at least one scan cell of the second plurality of scan cell is of a second cell type and at least one other scan cell of the second plurality of scan cell is of a third cell type. ### Claim 10 A non-transitory computer-readable medium that stores a set of instructions which when executed perform a method executed by the set of instructions comprising: transforming elements of a circuit under test into scan cells, wherein transforming the elements comprises enabling a scan input and a scan output for the elements; forming a first scan chain comprising a first plurality of scan cells of a first cell type, wherein forming the first scan chain comprises connecting the scan output of a first scan cell to the scan input of a second san cell; determining that the first cell type not to be a suspect for a systematic defect; swapping, one scan cell of the first scan chain with another scan cell of a second scan chain, wherein the another scan cell is of a second cell type; and testing, after the swapping, the first scan chain to determine a cell-dependent defect. ### Claim 11 (depends on 10) The non-transitory computer-readable medium of claim 10, wherein the method further comprising splitting the first scan chain into multiple scan chains when a number of the first plurality of scan cells is more than a predetermined number. ### Claim 12 (depends on 10) The non-transitory computer-readable medium of claim 10, wherein the method further comprising forming the first scan chain comprises forming the first scan chain comprising the first plurality of scan cells of the first cell type comprising a predetermined scan cell design. ### Claim 13 (depends on 10) The non-transitory computer-readable medium of claim 10, wherein the method further comprising forming the first scan chain comprises forming the first scan chain comprising the first plurality of scan cells of the first cell type comprising a suspect scan cell design. ### Claim 14 (depends on 10) The non-transitory computer-readable medium of claim 10, wherein the method further comprising incrementally mixing at least one scan cell of a different cell type into the first scan chain. ### Claim 15 (depends on 10) The non-transitory computer-readable medium of claim 10, wherein the method further comprising: masking the scan cells of the first cell type; and determining whether a second plurality of scan cells of a second cell type contain the systematic defect. ### Claim 16 (depends on 10) The non-transitory computer-readable medium of claim 10, wherein the circuit under the test is obtained from a first die, and wherein the method further comprising: determining the systematic defect for the circuit under test obtained from at least one second die; and aggregating the suspect obtained for the circuit under test obtained from the at least one second die with the suspect for the circuit under test obtained from the first die. ### Claim 17 An apparatus for determining a systematic defect in a circuit under test, the apparatus comprising: a memory storage; and a processing unit coupled to the memory storage, wherein the processing unit is operative to: form a first scan chain comprising a first plurality of scan cells, wherein each scan cell of the first plurality of scan cells of the first scan chain are of a first cell type; determine whether the first cell type is a suspect for a systematic defect; mask, in response to determining that the first cell type is not a suspect for the systematic defect, the first plurality of scan cells of the first scan chain; form a second scan chain comprising a second plurality of scan cells, wherein the second scan chain comprises of at least one scan cell of a second cell type; and determine that the second scan chain is a suspect for the systematic defect. ### Claim 18 (depends on 17) The apparatus of claim 17, wherein the second scan chain comprises mixed scan cells of the first cell type and the second cell type. ### Claim 19 (depends on 17) The apparatus of claim 17, wherein the processor being further operative to convert elements of the circuit under test into the first plurality of scan cells and the second plurality of can cells. ### Claim 20 (depends on 17) The apparatus of claim 17, wherein the first cell type comprises a suspect scan cell design based on a prior testing.