Supply voltage and temperature independent receiver

A method comprising:

• receiving an input voltage signal at an input node;
• generating, at a first inverter circuit of a first switching threshold voltage connected between the input node and an output node, a first output signal by applying the input voltage signal to a first set of one or more core circuits each of which includes a complementary metal-oxide-semiconductor (CMOS) transistor of a first type and a CMOS transistor of a second type having a first common gate node connected to the input node and a first common drain node connected to the output node;
• generating, at a second inverter circuit of a second switching threshold voltage lower than the first switching threshold voltage connected between the input node and the output node, a second output signal by applying the input voltage signal to a second set of one or more core circuits each of which includes a CMOS transistor of a third type and a CMOS transistor of a fourth type having a second common gate node connected to the input node and a second common drain node connected to the output node;
• and
• generating an output voltage signal at the output node by combining the first output signal and the second output signal.

An electronic device, comprising:

• an interfacing bus;
• a first integrated circuit connected to the interfacing bus;
• and
• a second integrated circuit connected to the interfacing bus, the second integrated circuit comprising a circuitry, the circuitry comprising:
• an input node configured to receive an input voltage signal,
• an output node configured to output an output voltage signal,
• a first inverter circuit of a first switching threshold voltage, the first inverter circuit connected between the input node and the output node, the first inverter circuit including a first set of one or more core circuits, each core circuit of the first set including a complementary metal-oxide-semiconductor (CMOS) transistor of a first type and a CMOS transistor of a second type having a first common gate node connected to the input node and a first common drain node connected to the output node, and
• a second inverter circuit of a second switching threshold voltage lower than the first switching threshold voltage, the second inverter circuit connected between the input node and the output node, the second inverter circuit including a second set of one or more core circuits, each core circuit of the second set including a CMOS transistor of a third type and a CMOS transistor of a fourth type having a second common gate node connected to the input node and a second common drain node connected to the output node.