# US 10,865,103 B2 · Packaging method and associated packaging structure

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- Number: US 10,865,103 B2
- Document ID: US10865103B2
- Status: Granted
- Kind: B2
- Application number: 16/046,651
- Filed: 2018-07-26
- Published: 2019-04-04
- Granted: 2020-12-15
- Earliest claimed: 2015-12-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Chih-Ming Chen; Yuan-Chih Hsieh; Chung-Yi Yu
- Web page: https://patentgrep.com/patent/US10865103B2

## CPC

- B81C 1/00269: {Bonding of solid lids or wafers to the substrate}
- B81B 7/0041: {maintaining a controlled atmosphere with techniques not provided for in B81B7/0038}
- B81C 1/00: Manufacture or treatment of devices or systems in or on a substrate (B81C3/00 takes precedence)
- B81C 1/00238: {Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 90/00: Package configurations
- B81B 2201/0235: Accelerometers
- B81B 2201/0242: Gyroscopes
- B81B 2201/0264: Pressure sensors
- B81B 2207/012: the micromechanical device and the control or processing electronics being separate parts in the same package
- B81B 2207/093: Conductive package seal
- B81C 2201/0132: Dry etching, i.e. plasma etching, barrel etching, reactive ion etching [RIE], sputter etching or ion milling
- B81C 2201/019: Bonding or gluing multiple substrate layers
- B81C 2203/0118: Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
- B81C 2203/035: Soldering
- B81C 2203/036: Fusion bonding
- H10W 72/072: {of bump connectors}
- H10W 72/90: Bond pads, in general
- B81C: PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS (making microcapsules or microballoons B01J13/02; processes or apparatus specially adapted for the manufacture or treatment of piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/01)
- B81B: MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES (piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/00, H10N35/00)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn). An associated packaging structure is also disclosed.

## Claims

### Claim 1

A packaging structure, comprising:
a first semiconductor substrate having a first semiconductor portion that is disposed over and extends from a second semiconductor portion, wherein a first width of the first semiconductor portion is less than a second width of the second semiconductor portion;
a second semiconductor substrate having a dielectric layer and a first copper bonding layer, wherein a bonding area of the second semiconductor substrate is defined by a first sidewall of the dielectric layer, a second sidewall of the dielectric layer, and the first copper bonding layer, and further wherein the first copper bonding layer is disposed in and physically contacts the dielectric layer, the first copper bonding layer extends from the first sidewall of the dielectric layer to the second sidewall of the dielectric layer, a topmost surface of the dielectric layer is higher than a topmost surface of the first copper bonding layer, a third width is defined between the first sidewall of the dielectric layer and the second sidewall of the dielectric layer;
a bonding interface layer disposed directly on and physically contacting the first copper bonding layer and further disposed between the first sidewall of the dielectric layer and the second sidewall of the dielectric layer, wherein the bonding interface layer includes Cu3Sn, a topmost surface of the bonding interface layer is lower than the topmost surface of the dielectric layer, and a fourth width of the bonding interface layer is less than the third width defined between the first sidewall of the dielectric layer and the second sidewall of the dielectric layer, such that the bonding interface layer is spaced away from and does not physically contact the first sidewall and the second sidewall of the dielectric layer;
a second copper bonding layer disposed directly on and physically contacting the bonding interface layer and further disposed between the first sidewall of the dielectric layer and the second sidewall of the dielectric layer, wherein the second copper bonding layer is disposed between the first semiconductor portion of the first semiconductor substrate and the bonding interface layer, and further wherein a fifth width of the second copper bonding layer is less than the third width defined between the first sidewall of the dielectric layer and the second sidewall of the dielectric layer, such that the second copper bonding layer is spaced away from and does not physically contact the first sidewall and the second sidewall of the dielectric layer;
wherein each of the fourth width of the bonding interface layer and the fifth width of the second copper bonding layer is substantially the same as the first width of the first semiconductor portion of the first semiconductor substrate; and
wherein the first copper bonding layer, the bonding interface layer, and the second copper bonding layer form a bonding structure that attaches the first semiconductor substrate to the second semiconductor substrate and provides an electrical path between a first device of the first semiconductor substrate and a second device of the second semiconductor substrate.

### Claim 2 (depends on 1)

The packaging structure of claim 1, wherein a sixth width of the first copper bonding layer is greater than the fourth width of the bonding interface layer and the fifth width of the second copper bonding layer.

### Claim 3 (depends on 1)

The packaging structure of claim 1, wherein the first device is a MEMs device and the second device is a transistor.

### Claim 4 (depends on 3)

The packaging structure of claim 3, wherein the first semiconductor portion of the first semiconductor substrate is disposed between the first sidewall of the dielectric layer and the second sidewall of the dielectric layer, and further wherein the first width of the first semiconductor portion of the first semiconductor substrate is less than the third width defined between the first sidewall of the dielectric layer and the second sidewall of the dielectric layer, such that first semiconductor portion is spaced away from and does not physically contact the first sidewall and the second sidewall of the dielectric layer.

### Claim 5 (depends on 1)

The packaging structure of claim 1, wherein the dielectric layer and the first copper bonding layer are a portion of a multi-layer interconnect structure of the second semiconductor substrate.

### Claim 6 (depends on 1)

The packaging structure of claim 1, wherein a thickness of the bonding interface layer is greater than a thickness of the second copper bonding layer.

### Claim 7 (depends on 1)

The packaging structure of claim 1, wherein a topmost surface of the second copper bonding layer is lower than the topmost surface of the dielectric layer.

### Claim 8

A device comprising:
a MEMS wafer having a first surface and a second surface opposite the first surface, wherein a first bonding mesa and a second bonding mesa protrude from the first surface of a first portion and a second portion, respectively, of the MEMS wafer and a MEMS device of the MEMS wafer is disposed between the first bonding mesa and the second bonding mesa;
a transistor wafer having a third surface and a fourth surface opposite the third surface, wherein a multilayer interconnect (MLI) is disposed over the third surface of the transistor wafer; and
an eutectic bonding structure that attaches the first bonding mesa and the second bonding mesa to the MLI and provides an electrical path between the transistor wafer and the MEMS device, wherein the first bonding mesa and the second bonding mesa protrude from the first surface of the first portion and the second portion, respectively, of the MEMS wafer towards the third surface of the transistor wafer, wherein the eutectic bonding structure includes:
a patterned first copper layer,
a patterned second copper layer, and
an eutectic alloy layer disposed between and physically contacting the first patterned copper layer and the second patterned copper layer, wherein the eutectic alloy layer includes copper (Cu) and tin (Sn), wherein the first patterned copper layer is disposed between topmost surfaces of the first bonding mesa and the second bonding mesa and the eutectic alloy layer and the second patterned copper layer is disposed between a first metal layer and a second metal layer of the MLI and the eutectic alloy layer.

### Claim 9 (depends on 8)

The device of claim 8, wherein:
a first width of the first patterned copper layer disposed between the topmost surface of the first bonding mesa and the eutectic alloy layer is substantially the same as a second width of the first bonding mesa; and
a third width of the first patterned copper layer disposed between the topmost surface of the second bonding mesa and the eutectic alloy layer is substantially the same as a fourth width of the second bonding mesa.

### Claim 10 (depends on 8)

The device of claim 8, wherein:
a first width of the first bonding mesa is less than a second width of the first portion of the MEMS wafer from which the first bonding mesa protrudes from the first surface; and; and
a third width of the second bonding mesa is less than a fourth width of the second portion of the MEMS wafer from which the second bonding mesa protrudes from the first surface.

### Claim 11 (depends on 8)

The device of claim 8, further comprising a cap substrate attached to the second surface of the MEMS wafer by a dielectric layer.

### Claim 12 (depends on 8)

The device of claim 8, wherein the eutectic alloy layer is free of unreacted Sn.

### Claim 13 (depends on 8)

The device of claim 8, wherein the second patterned copper layer is a portion of the MLI, wherein the second patterned copper layer is disposed within a topmost dielectric layer of the MLI, and wherein a top surface of the second patterned copper layer is lower than a top surface of the topmost dielectric layer of the MLI.

### Claim 14 (depends on 8)

The device of claim 8, wherein the eutectic bonding structure further includes a titanium layer disposed between the patterned first copper layer and the topmost surfaces of the first bonding mesa and the second bonding mesa.

### Claim 15

A device comprising:
an engineered silicon-on-insulator (ESOI) wafer that includes:
a cap substrate, and
a sensing substrate attached to the cap substrate by fusion bonding, wherein
the sensing substrate includes a MEMS device disposed between a first bonding mesa and a second bonding mesa extending from the sensing substrate; and
a complementary metal-oxide-semiconductor (CMOS) wafer that includes a transistor and a multilayer interconnect (MLI) disposed over the transistor, wherein the CMOS wafer is attached to the ESOI wafer by eutectic bonding, wherein the eutectic bonding is achieved by:
a first metal bonding layer disposed on the first bonding mesa and a second metal bonding layer disposed on the second bonding mesa,
a third metal bonding layer and a fourth metal bonding layer that are a portion of the MLI of the CMOS wafer, and
a metal alloy bonding interface layer disposed between the first metal bonding layer and the third metal bonding layer and the second metal bonding layer and the fourth metal bonding layer, wherein the metal alloy bonding interface layer is a Cu3Sn layer.

### Claim 16 (depends on 15)

The device of claim 15, wherein the first metal bonding layer, the second metal bonding layer, the third metal bonding layer, and the fourth metal bonding layer include the same material.

### Claim 17 (depends on 15)

The device of claim 15, wherein the first metal bonding layer and the second metal bonding layer each include a titanium layer disposed directly on the first bonding mesa and the second bonding mesa, respectively, and a copper layer disposed directly on the titanium layer, such that the copper layer physically contacts the titanium layer and the metal alloy bonding interface layer.

### Claim 18 (depends on 15)

The device of claim 15, wherein the metal alloy bonding interface layer is free of unreacted Sn.

### Claim 19 (depends on 15)

The device of claim 15, wherein the second metal bonding layer is a topmost conductive layer of the Mil of the CMOS wafer.

### Claim 20 (depends on 15)

The device of claim 15, further comprising:
a third bonding mesa and a fourth bonding mesa that interpose the first bonding mesa and the second bonding mesa, wherein the eutectic bonding is further achieved by:
a fifth metal bonding layer disposed on the third bonding mesa and a sixth metal bonding layer disposed on the second bonding mesa,
a seventh metal bonding layer and an eighth metal bonding layer that are a portion of the MLI of the CMOS wafer, and
wherein the metal alloy bonding interface layer is further disposed between the fifth metal bonding layer and the seventh metal bonding layer and the sixth metal bonding layer and the eighth metal bonding layer.