Arbitrary rate decimator and timing error corrector for an FSK receiver

A variable rate decimation module, comprising circuitry configured to implement:

• a plurality of cascaded power-of-two decimator stages connected to receive a digital data stream at an input sampling rate and to generate a first filtered digital signal;
• and
• a fractional resampling stage connected to receive the first filtered digital signal and to generate a second filtered digital signal at an output sampling rate;
• wherein each of the plurality of cascaded power-of-two decimator stages is configured to decimate a sampling rate for a received digital input signal by a specified power-of-two factor which may be identical to or different from a specified power-of-two factor used by another of the plurality of cascaded power-of-two decimator stages;
• and
• wherein the fractional resampling stage comprises:
• a delta-sigma modulator connected to generate a modulated desired rate change signal in response to a first control word,
• a limited integrator stage connected to generate a time shift command signal and a pulse swallow/insert command signal in response to the modulated desired rate change signal and a modified clock signal,
• a clock generator connected to generate the modified clock signal in which clock pulses are swallowed or inserted in response to the pulse swallow/insert command signal, and
• a timing shift filter connected to receive the modified clock signal and the time shift command signal and to perform fractional interpolation on the first filtered digital signal to generate the second filtered digital signal.

A method comprising:

• receiving a digital data stream from an analog-to-digital converter at a source input;
• generating a first filtered digital signal from the digital data stream using a plurality of cascaded power-of-two decimator stages, wherein each power-of-two decimator stage is configured to decimate a sampling rate for a received digital input signal by a specified power-of-two;
• and
• generating a second filtered digital signal from the first filtered digital data stream using a fractional resampler comprising a delta-sigma modulator and a limited integrator stage connected to receive a first control word and a feedback clock signal with inserted or swallowed pulses which is generated by a clock generator in response to pulse commands generated by the limited integrator stage, wherein the limited integrator is configured to generate time shift commands to a timing shift filter which is configured to decimate a sampling rate for the first filtered digital signal by an arbitrary decimation rate, thereby generating the second filtered digital signal.