Electronic assembly that includes void free holes

#This application is a U.S. National Stage Filing under 35 U.S.C. 371 from International Application No. PCT/US2015/052446, filed on Sep. 25, 2015, and published as WO 2017/052642, which application is incorporated herein by reference in its entirety.

#There are two conventional approaches for forming copper patterns on core layers. A typical copper pattern includes copper traces on both sides of the core and copper filled through hole vias that extend thorough the core.

#One known patterning technique involves covering both sides of the core with electrolytic copper and also filling a laser drilled through hole in the core with the electrolytic copper. Both sides of the core are then subtractive patterned and etched in order to form conductive traces on both sides of the core.

#FIG. 1 is a schematic side view illustrating a prior art electronic assembly that includes through holes with voids.

#FIG. 2 is a schematic side view illustrating an example electronic assembly that includes through holes without voids.

#FIG. 3 is a process flow table that compares a prior art electronic assembly fabrication method with an example electronic assembly fabrication method.

#The following description and the drawings sufficiently illustrate specific embodiments to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Embodiments set forth in the claims encompass all available equivalents of those claims.

#Orientation terminology, such as “horizontal,” as used in this application is defined with respect to a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizontal as defined above. Prepositions, such as “on,” “side” (as in “sidewall”), “higher,” “lower,” “over,” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate.

#The electronic assemblies and method may overcome the drawbacks that are associated with the prior art electronic assemblies and methods. The electronic assemblies and methods described herein produce void-free vias.