Transmission line design with routing-over-void compensation

A system comprising:

• a substrate including a reference plane structure;
• a first integrated circuit chip mounted to the substrate;
• a second integrated circuit chip;
• and
• a signal conductor mounted to the substrate, the signal conductor configured to couple between the first chip and the second chip and to span a void in the reference plane structure, the signal conductor comprising:
• a first part routed over the major surface of a first side of the void and that approaches a first edge of the reference plane structure with a first trajectory;
• a second part routed over the major surface of a second side of the void and that approaches a second edge of the reference plane structure with a second trajectory in-line with the first trajectory;
• a third portion connecting the first portion with the second portion and having a “U”-shape or an “S”-shape, the third portion configured to span the void;
• and
• wherein the reference plane structure includes:
• a first reference plane including the first edge and configured to be at a first reference potential;
• and
• a second reference plane including the second edge and configured to be at a second reference potential different from the first reference potential.