Semiconductor device including a high-speed receiver being capable of adjusting timing skew for multi-level signal and testing equipment including the receiver

A semiconductor device comprising:

• a comparator circuit configured to receive a first analog signal having m signal levels and compare the first analog signal with m−1 reference signals to generate first and second digital signals, receive a second analog signal having m signal levels and compare the second analog signal with the m−1 reference signals to generate third and fourth digital signals;
• and
• a timing skew adjusting circuit configured to compensate for a timing skew between the first analog signal and the second analog signal, using the first to fourth digital signals,
• wherein m is a natural number >=3,
• wherein the timing skew adjusting circuit includes:
• a decoding circuit which performs a predefined operation on the digital signals to generate and output first and second output signals;
• and
• a timing skew adjusting circuit which controls the decoding circuit to output the first and second output signals in which the timing skew between the analog signals is compensated, using the digital signals,
• wherein the decoding circuit includes:
• an OR gate circuit which executes an OR operation on pairs of the digital signals;
• and
• a flip-flop circuit which receives outputs of the OR gate circuit and outputs the first and second output signals at a predefined timing, and
• wherein the timing skew adjusting circuit controls an output timing of the flip-flop circuit, using outputs of the OR gate circuit.

Semiconductor testing equipment comprising:

• a receiver configured to receive first and second multi-level signals from a circuit, convert the first and second multi-level signals into a plurality of single level signals, and generate an output signal using the plurality of single level signals;
• and
• a tester configured to test the circuit using the output signal,
• wherein each of the first and second multi-level signals has m levels, where m is a natural number >=3,
• wherein each of the single level signals has two levels, and
• wherein the receiver compensates for a timing skew of the first and second multi-level signals using the plurality of single level signals to generate the output signal,
• wherein the receiver comprises:
• a decoding circuit which performs a predefined operation on the single level signals to generate and output first and second output signals;
• and
• a timing skew adjusting circuit which controls the decoding circuit to output the first and second output signals in which the timing skew between the first and second multi-level signals is compensated, using the single level signals,
• wherein the decoding circuit includes:
• an OR gate circuit which executes an OR operation on pairs of the single level signals;
• and
• a flip-flop circuit which receives outputs of the OR gate circuit and outputs the first and second output signals at a predefined timing, and
• wherein the timing skew adjusting circuit controls an output timing of the flip-flop circuit, using outputs of the OR gate circuit.