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US 10,855,496 B2Granted
Edge based partial response equalization
AssigneeRambus Inc.
InventorsBrian S. Leibowitz, Hae-Chang Lee, Jihong Ren, Ruwan Ratnayake
Life of this patent
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Abstract
An integrated circuit (IC) memory device includes receiver circuitry to receive write data from a memory controller. The receiver circuitry includes equalization circuitry having at least one tap to equalize the write data. The equalization circuitry includes a tap weight adapter circuit to adaptively generate a tap weight for the tap from an edge analysis of previously received write data.
Claims19
An integrated circuit (IC) memory device comprising:
- receiver circuitry to receive write data from a memory controller, the receiver circuitry including
- equalization circuitry having at least one tap to equalize the write data, the equalization circuitry including a tap weight adapter circuit to adaptively generate a tap weight for the tap from an edge analysis of previously received write data.
An integrated circuit (IC) memory device comprising:
- circuitry to interface with a memory controller via multiple links, the circuitry including multiple receivers, each receiver to receive write data via a corresponding link and comprising
- an equalizer having at least one tap to apply equalize the write data in accordance with an equalizer coefficient corresponding to the at least one tap;
- and
- a tap weight adapter circuit to adaptively generate the equalizer coefficient from edge-based sampling information associated with prior received write data.
1 more element
A method of operation in an integrated circuit (IC) memory device, the method comprising:
- receiving write data from a memory controller, the receiving including
- applying data level equalization to the write data with at least one tap of an equalizer, and
- adaptively generating a tap weight for the at least one tap based on an edge analysis of previously received write data.
Dependencies are inferred from the claim text.