Characterization of in-chip error correction circuits and related semiconductor memory devices/memory systems
AssigneeSamsung Electronics Co., Ltd.
InventorsHoi-Ju Chung, Sang-Uhn Cha, Hyun-Joong Kim
Life of this patent
Estimating the term…
Abstract
A method of operating a semiconductor memory device can include receiving data, from a memory controller, at an Error Correction Code (ECC) engine included in the semiconductor memory device, the data including at least one predetermined error. Predetermined parity can be received at the ECC engine, where the predetermined parity is configured to correspond to the data without the at least one predetermined error. A determination can be made whether a number of errors in the data is correctable by the ECC engine using the data including the at least one predetermined error and the predetermined parity.
Claims7
A memory system comprising:
- at least one semiconductor memory device;
- and
- a memory controller configured to control the at least one semiconductor memory device, wherein the at least one semiconductor memory device comprises:
- a memory cell array;
- an error correction circuit configured to perform an error correction code (ECC) decoding based on data read from the memory cell array in a normal mode;
- and
- a control logic circuit configured to control access to the memory cell array and configured to control the error correction circuit in response to a command from the memory controller,
- wherein the error correction circuit is configured to perform the ECC decoding on a first error vector from the memory controller and configured to output a second error vector indicating a result of the ECC decoding when the command directs a code validation mode to test an ECC implemented in the error correction circuit and the first error vector includes at least one predetermined error bit.
Dependencies are inferred from the claim text.