Parallelized successive interference cancellation (PSiC) receiver architecture for wireless communications systems

A wireless receiver, comprising:

• a signal encoding module configured to encode a plurality of received analog signals with an orthogonal code set and combine the encoded analog signals into a single encoded analog composite signal;
• an analog-to-digital conversion unit configured to convert the single encoded analog composite signal into a single encoded digital composite signal containing constituent digital signals;
• a plurality of banks comprising successive interference cancellation (SiC) modules, each of the SiC banks including multiple SiC modules configured to sequentially remove the constituent digital signals from the single encoded digital composite signal until, for each of the SiC banks, a different single constituent digital signal remains, wherein each of the multiple SiC modules within each SiC bank is configured to remove a respective one of the constituent digital signals and to provide a succeeding SiC module the single encoded digital composite signal without the removed respective one constituent digital signal;
• and
• a plurality of decoding modules, each of the decoding modules operative to receive the single encoded digital composite signal from a corresponding SiC bank and configured to decode the remaining constituent digital signal from the single encoded digital composite signal for each of the SiC banks.