High-speed, low power, low kickback noise comparator suitable for a multi-comparator successive approximation analog-to-digital converter (ADC)

Abstract

A comparator is described. The comparator includes a differential pair having first and second transistors to respectively receive first and second input signals. The comparator also includes a current sink or source transistor coupled to respective source nodes of the first and second transistors. The current sink or source transistor is coupled to receive a fixed bias to keep the current sink transistor active so that large voltage changes on the source nodes is avoided. The comparator circuit includes a latch circuit coupled to respective drain nodes of the first and second transistors. The latch circuit is to reach a final state to present the comparator's output signal. The comparator includes a first switch circuit coupled between the first transistor's drain node and the latch circuit, and a second switch circuit coupled between the second transistor's drain node and the latch circuit. The first and second switch circuits to allow the first and second transistors' respective drain node voltage and source node voltage to enter and exit the comparator's comparison state at a same voltage.

Dependencies are inferred from the claim text.