Track and hold circuits for high speed and interleaved ADCs
AssigneeAnalog Devices, Inc.
InventorAhmed Mohamed Abdelatty Ali
Life of this patent
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Abstract
Improved track and hold (T/H) circuits can help analog-to-digital converters (ADCs) achieve higher performance and lower power consumption. The improved T/H circuits can drive high speed and interleaved ADCs, and the design of the circuits enable additive and multiplicative pseudo-random dither signals to be injected in the T/H circuits. The dither signals can be used to calibrate (e.g., linearize) the T/H circuits and the ADC(s). In addition, the dither signal can be used to dither any remaining non-linearity, and to calibrate offset/gain mismatches in interleaved ADCs. The T/H circuit design also can integrate an amplifier in the T/H circuit, which can be used to improve the signal-to-noise ratio (SNR) of the ADC or to act as a variable gain amplifier (VGA) in front of the ADC.
Claims20
A circuit comprising:
- a plurality of analog-to-digital converter (ADC) slices;
- a first signal pathway that includes a first sampling network, wherein the first signal pathway is selectively couplable to the plurality of ADC slices by a first switch;
- and
- a second signal pathway that includes a second sampling network, wherein the second signal pathway is selectively couplable to a first subset of the plurality of ADC slices;
- and
- a third signal pathway that includes a third sampling network, wherein the third signal pathway is selectively couplable to a second subset of the plurality of ADC slices, wherein the second subset is different than the first subset.
An electronic device comprising:
- a plurality of signal inputs;
- a plurality of analog-to-digital converter (ADC) slices;
- a first signal pathway communicatively positioned between the signal input and the plurality of ADC slices, wherein the first signal pathway includes a first sampling network and a first input buffer;
- a second signal pathway communicatively positioned between the signal input and a first subset of the plurality of ADC slices, wherein the second signal pathway includes a second sampling network and a second input buffer;
- and
- a third signal pathway communicatively positioned between the signal input and a second subset of the plurality of ADC slices, wherein the third signal pathway includes a third sampling network and a third input buffer;
- wherein the first subset differs from the second subset.
A reconfigurable analog-to-digital converter (ADC), comprising:
- a plurality of signal inputs;
- a plurality of ADC slices;
- a plurality of sampling networks positioned between the plurality of signal inputs and the plurality of ADC slices;
- and
- a plurality of switches controllable to:
- (1) communicably connect a single one of the plurality of signal inputs via one or more sampling networks to the plurality of ADC slices, and
- (2) communicably connect a first one of the plurality of signal inputs via a first one of the sampling networks to a first subset of the plurality of ADC slices, and communicably connect a second one of the plurality of signal inputs via a second one of the sampling networks to a second subset of the plurality of ADC slices, wherein the first subset and the second subset are different.
Dependencies are inferred from the claim text.