Phase locked loop

A phase-locked loop (PLL), comprising:

• a voltage-controlled oscillator (VCO) configured to provide an output clock according to a control voltage;
• a low pass filter (LPF) configured to filter a pumping signal corresponding to a pumping current to provide the control voltage;
• a track-and-hold charge pump input coupled to the LPF and configured to provide the pumping current according to a reference signal and a feedback signal corresponding to the output clock;
• and
• a bandwidth calibration circuit coupled to the LPF and configured to provide a control signal to the track-and-hold charge pump, so as to adjust the pumping current.

A phase-locked loop (PLL), comprising:

• a voltage-controlled oscillator (VCO) configured to provide an output clock according to a control voltage;
• a low pass filter (LPF) configured to filter a pumping signal corresponding to a pumping current to provide the control voltage;
• a frequency divider configured to divide the output clock to provide a feedback signal;
• and
• a track-and-hold charge pump coupled to the LPF and configured to provide the pumping current according to a reference clock and the feedback signal;
• wherein the track-and-hold charge pump comprises:
• a track-and-hold circuit configured to sample the feedback signal according to the reference clock;
• a transconductance amplifier configured to convert the sampled feedback signal into a current;
• a pulse width modulator (PWM) configured to provide a PWM signal according to the reference clock;
• and
• a pumping switch coupled between the transconductance amplifier and the LPF,
• wherein the pumping switch is controlled by the PWM signal, to provide the pumping current according to the current.