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US 10,855,290 B1Granted
Delay locked loop
AssigneesSK hynix Inc., Korea University Research and Business Foundation
InventorsChul Woo Kim, Hyun Su Park
Life of this patent
Estimating the term…
Abstract
Embodiments disclose a delay locked loop. The delay locked loop including a main delay circuit configured to generate initial clocks by delaying an internal clock, and sub-delay lines configured to generate phase clocks having a phase difference corresponding to a desired initial delay by respectively delaying the internal clock and the initial clocks. The phase difference among the phase clocks may be adjusted according to delay values of the sub-delay lines.
Claims9
A delay locked loop comprising:
- a main delay circuit configured to generate a plurality of initial clocks by delaying an internal clock, the main delay circuit including a plurality of unit delay lines, wherein each of the plurality of unit delay lines includes a respective coarse delay line and a respective fine delay line;
- and
- a plurality of sub-delay lines configured to generate a plurality of phase clocks having a phase difference corresponding to a desired initial delay by respectively delaying the internal clock and the initial clocks,
- wherein the phase difference among the phase clocks is adjusted according to delay values of the plurality of sub-delay lines,
- wherein the sub-delay lines are set to have delay values depending on a mode, the mode being a high speed mode, a normal mode, or a lower power mode,
- wherein in the high speed mode, the plurality of sub-delay lines are set to have delay values that decrease by a predetermined value from N times an initial delay value of the coarse delay line of the main delay circuit in sequence of the phase clocks, where N is an integer,
- wherein in the lower power mode, the plurality of sub-delay lines are set to have delay values that increase by a predetermined value from an initial delay value of the coarse delay line of the main delay circuit in sequence of the phase clocks, and
- wherein in the normal mode, the plurality of sub-delay lines are set to have an initial delay value of the coarse delay line of the main delay circuit.
5 more elements
A delay locked loop comprising:
- a main delay circuit configured to generate first, second, third, and fourth initial clocks by delaying an internal clock, the main delay circuit including first, second, third, and fourth unit delay lines, wherein each of the first, second, third, and fourth unit delay lines includes a respective coarse delay line and a respective fine delay line;
- and
- a sub-delay circuit configured to generate first, second, third, and fourth phase clocks having a phase difference according to a desired initial delay by respectively delaying the internal clock and the first to third initial clocks by first, second, third, and fourth delay values,
- wherein the first to fourth delay values are used to adjust the phase difference according to the initial delay,
- wherein the delay values of the first to fourth sub-delay lines are set depending on a mode, the mode being a high speed mode, a normal mode, or a lower power mode,
- wherein in the high speed mode, the first to fourth sub-delay lines are set to have delay values that decrease by a predetermined value from N times an initial delay value of the coarse delay line of the main delay circuit in sequence of the phase clocks, where N is an integer,
- wherein in the lower power mode, the first to fourth sub-delay lines are set to have delay values that increase by a predetermined value from an initial delay value of the coarse delay line of the main delay circuit in sequence of the phase clocks, and
- wherein in the normal mode, the first to fourth sub-delay lines are set to have an initial delay value of the coarse delay line of the main delay circuit.
5 more elements
Dependencies are inferred from the claim text.