Non-volatile multiple time programmable integrated circuit system with selective conversion to one time programmable or permanent configuration bit programming capabilities and related methods

An electric device comprising:

• a first signal input bus;
• a program signal input transistor and an erase signal input transistor coupled with the first signal input bus;
• a read enable transistor disposed between a VSS source and the first signal input bus that selectively supplies a VSS to inputs of a plurality of magnetic tunnel junction (MTJ) sections;
• a plurality of dielectric breakdown control circuitry sections comprising:
• a first dielectric breakdown control circuitry section that includes a first dielectric breakdown control transistor that selectively couples the VS S with a metalized resistor of a reference signal section;
• a second dielectric breakdown control circuitry section that comprises:
• a dielectric layer breakdown circuit voltage source input section that receives a dielectric breakdown voltage signal that causes said dielectric layer in one of said MTJ sections selected by a look up table (LUT) section and select bus line inputs to breakdown and thereby have a lower resistance than said dielectric layer had before said breakdown;
• and
• a second dielectric breakdown control transistor selectively couples the dielectric layer breakdown circuit voltage source input section to at least one of a plurality of programmable logic sections comprising respective said MTJ cell sections;
• a third dielectric breakdown control circuitry section that comprises a third dielectric breakdown control transistor, a first finalizing MTJ, and a second finalizing MTJ, wherein the third dielectric breakdown control transistor is coupled in parallel with the first finalizing MTJ, wherein the second finalizing MTJ is coupled with the second dielectric breakdown control circuitry section, wherein the third dielectric breakdown control transistor is selectively coupled with the VSS;
• and
• a fourth dielectric breakdown control circuitry section that comprises a fourth dielectric breakdown control transistor coupled with an output of the LUT section;
• wherein the first finalizing MTJ and the third dielectric breakdown control transistor is coupled with the VSS, wherein the first finalizing MTJ and the third dielectric breakdown control transistor is coupled with the second finalizing MTJ, wherein the second finalizing MTJ is coupled with the second dielectric breakdown control transistor and the first signal input bus;
• an isolation transistor coupled with the first signal input bus that selectively isolates the plurality of MTJ sections and the read enable transistor from the second dielectric breakdown control circuitry section, the third dielectric breakdown control circuitry section, and the program signal input transistor and the erase signal input transistor.

A field programmable gate array comprising:

• a first signal input bus;
• a plurality of programmable logic section comprising a plurality of magnetic tunnel junction (MTJ) cell sections and a corresponding programmable logic circuit look up table (LUT) section, wherein the LUT section comprises one or more select bus lines and a plurality of LUT transistors each coupled with one or more said select bus lines, wherein the LUT section selectively reads out a logic state of one of said MTJ cell sections based on inputs of the one or more select bus lines, wherein each said MTJ comprises a free magnetic layer, a dielectric layer adjacent to the free magnetic layer, and a pinned magnetic layer adjacent to the dielectric layer, wherein the LUT section further comprises a reference signal section, the reference signal section includes a reference signal MTJ coupled in series with a metalized resistor;
• a programmable MTJ logic state sensing section comprising a sense amplifier that selectively receives reference signals from the reference signal section and a LUT section output from the LUT section, wherein the LUT section is controlled by the one or more select bus lines selectively couples one of the MTJs with the programmable MTJ logic state sensing section to read out the logic state of a selected said MTJ cell section;
• a program signal input transistor and an erase signal input transistor coupled with the first signal input bus;
• a read enable transistor disposed between a VSS source and the first signal input bus that selectively supplies a VSS to said inputs of the plurality of MTJ sections;
• a plurality of dielectric breakdown control circuitry sections comprising:
• a first dielectric breakdown control circuitry section that includes a first dielectric breakdown control transistor that selectively couples the VSS with the metalized resistor of the reference signal section;
• a second dielectric breakdown control circuitry section that comprises:
• a dielectric layer breakdown circuit voltage source input section that receives a dielectric breakdown voltage signal that causes said dielectric layer in one of said MTJ sections selected by the LUT section and select bus line inputs to breakdown and thereby have a lower resistance than said dielectric layer had before said breakdown;
• and
• a second dielectric breakdown control transistor selectively couples the dielectric layer breakdown circuit voltage source input section to at least one of the plurality of programmable logic sections comprising respective said MTJ cell sections;
• a third dielectric breakdown control circuitry section that comprises a third dielectric breakdown control transistor, a first finalizing MTJ, and a second finalizing MTJ, wherein the third dielectric breakdown control transistor is coupled in parallel with the first finalizing MTJ, wherein the second finalizing MTJ is coupled with the second dielectric breakdown control circuitry section, wherein the third dielectric breakdown control transistor is selectively coupled with the VSS;
• and
• a fourth dielectric breakdown control circuitry section that comprises a fourth dielectric breakdown control transistor coupled with an output of the LUT section that is controlled to operate in coordination with the second dielectric breakdown control circuitry section to selectively pass the dielectric breakdown voltage signal from the second dielectric breakdown control circuitry section through a LUT section selected MTJ;
• wherein the first finalizing MTJ and the third dielectric breakdown control transistor is coupled with the VSS, wherein the first finalizing MTJ and the third dielectric breakdown control transistor is coupled with the second finalizing MTJ, wherein the second finalizing MTJ is coupled with the second dielectric breakdown control transistor and the first signal input bus;
• an isolation transistor coupled with the first signal input bus that selectively isolates the plurality of MTJ sections and the read enable transistor from the second dielectric breakdown control circuitry section, the third dielectric breakdown control circuitry section, and the program signal input transistor and the erase signal input transistor.