Process of routing tile-to-tile interconnects of an FPGA, and method of manufacturing an FPGA

A method of routing interconnects of an integrated circuit comprising a field programmable gate array including:

• (i) a first plurality of non-contiguous logic tiles, wherein each logic tile of the first plurality of logic tiles includes a logic tile interconnect network having a plurality of switches and a plurality of logic tile interconnects, (ii) a second plurality of non-contiguous logic tiles, wherein each logic tile of the second plurality of logic tiles includes a logic tile interconnect network having a plurality of switches and a plurality of logic tile interconnects, and (iii) a tile-to-tile interconnect network, having a plurality of tile-to-tile interconnects, each tile-to-tile interconnect having start/end points to interconnect the logic tile networks of the first plurality of logic tiles and the second plurality of logic tiles, the method comprising:
• routing a first plurality of tile-to-tile interconnects in the first plurality of non-contiguous logic tiles temporally in parallel, wherein the start/end point of each tile-to-tile interconnect of the first plurality of tile-to-tile interconnects in the first plurality of non-contiguous logic tiles is independent of the start/end point of the other tile-to-tile interconnects of in the first plurality of tile-to-tile interconnects;
• after routing the first plurality of tile-to-tile interconnects in a first plurality of non-contiguous logic tiles, routing a second plurality of tile-to-tile interconnects in the second plurality of non-contiguous logic tiles temporally in parallel, wherein the start/end point of each tile-to-tile interconnect of the first plurality of tile-to-tile interconnects in the second plurality of non-contiguous logic tiles is independent of the start/end point of the other tile-to-tile interconnects in of the second plurality of tile-to-tile interconnects;
• and
• wherein routing the second plurality of tile-to-tile interconnects in the second plurality of non-contiguous logic tiles includes connecting at least one start/end point of each tile-to-tile interconnect in of the second plurality of tile-to-tile interconnects that was routed in the second plurality of logic tiles to at least one start/end point of a tile-to-tile interconnect of the first plurality of tile-to-tile interconnects that was routed in the first plurality of non-contiguous logic tiles to provide an interconnect path therebetween.

A method of routing interconnects of an integrated circuit comprising a field programmable gate array including:

• (i) a first plurality of non-contiguous logic tiles, wherein each logic tile of the first plurality of logic tiles includes a logic tile interconnect network having a plurality of switches and a plurality of logic tile interconnects, (ii) a second plurality of non-contiguous logic tiles, wherein each logic tile of the second plurality of logic tiles includes a logic tile interconnect network having a plurality of switches and a plurality of logic tile interconnects, and (iii) a tile-to-tile interconnect network, having a plurality of tile-to-tile interconnects, each tile-to-tile interconnect having start/end points to interconnect the logic tile networks of the first plurality of logic tiles and the second plurality of logic tiles, the method comprising:
• routing a first plurality of tile-to-tile interconnects in the first plurality of non-contiguous logic tiles, wherein the start/end point of each tile-to-tile interconnect in the first plurality of non-contiguous logic tiles is independent of the start/end point of the other tile-to-tile interconnects in of the first plurality of tile-to-tile interconnects, wherein a portion of the first plurality of tile-to-tile interconnects in the first plurality of non-contiguous logic tiles are routed sequentially;
• after routing the first plurality of tile-to-tile interconnects in a first plurality of non-contiguous logic tiles, routing a second plurality of tile-to-tile interconnects in the second plurality of non-contiguous logic tiles, wherein the start/end point of each tile-to-tile interconnect in the second plurality of logic tiles is independent of the start/end point of the other tile-to-tile interconnects in of the second plurality of tile-to-tile interconnects, wherein a portion of the second plurality of tile-to-tile interconnects in the second plurality of non-contiguous logic tiles are routed sequentially;
• and
• wherein routing the second plurality of tile-to-tile interconnects in the second plurality of non-contiguous logic tiles includes connecting at least one start/end point of each tile-to-tile interconnect in of the second plurality of tile-to-tile interconnects to at least one start/end point of a tile-to-tile interconnect of the first plurality of tile-to-tile interconnects that was routed in the first plurality of non-contiguous logic tiles to provide an interconnect path therebetween.