Buffer circuit
AssigneeMicron Technology, Inc.
InventorsHiroki Hosaka, Satoru Sugimoto, Hayato Oishi
Life of this patent
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Abstract
Apparatuses for providing buffer circuits a semiconductor device are described. An example apparatus includes a plurality of inverters and a transistor having one diffusion region coupled to a diffusion region of a transistor of one inverter of the plurality of inverters, another diffusion region coupled to a diffusion region of a transistor of another inverter of the plurality of inverters. The transistor having a gate coupled to one power supply voltage and diffusion regions coupled to another power supply voltage functions as a power voltage compensation capacitor.
Claims19
An apparatus comprising:
- a first transistor of a first type including a first gate, a first source region and a first drain region;
- a second transistor of the first type including a second gate, a second source region and a second drain region;
- a third transistor of the first type including a third gate, a third source region and a third drain region;
- and
- an electrode including the first gate and the second gate,
- wherein the first source region is coupled to the second source region, and
- wherein the third source region is coupled to the second drain region.
An apparatus comprising:
- a first transistor of a first type;
- a second transistor of the first type;
- a layer including:
- a region;
- and
- a first electrode over the region, the first electrode including a gate of the first transistor and the gate of the second transistor,
- wherein the layer is a first layer and further comprising a second layer on the first layer, wherein the second layer is a conductive layer.
An apparatus comprising:
- a first transistor;
- a second transistor;
- a first layer including:
- a region;
- and
- a first electrode over the region, the first electrode including a gate of the first transistor and the gate of the second transistor;
- a second layer on the first layer, the second layer is a conductive layer and includes an interconnect coupled to the first electrode;
- and
- an inverter including the first transistor and a third transistor, wherein the interconnect is a first interconnect and the second layer further includes the first interconnect and a second interconnect,
- wherein the second interconnect s coupled to a drain of the first ra sistor and a drain of the third transistor.
An apparatus comprising:
- a first transistor;
- a second transistor;
- a first layer including:
- a region;
- and
- a first electrode over the region, the first electrode including a gate of the first transistor and the gate of the second transistor;
- and
- a second layer on the first layer, the second layer is a conductive layer and includes an interconnect coupled to the first electrode,
- wherein the interconnect is a first interconnect and the second layer further includes the first interconnect and a second interconnect,
- wherein the second interconnect is configured to couple a gate of the third transistor to a source region of the first transistor, a source region of the second transistor.
An apparatus comprising:
- a first transistor;
- a second transistor;
- a first layer including:
- a region;
- and
- a first electrode over the region, the first electrode including a gate of the first transistor and the gate of the second transistor;
- a second layer on the first layer, the second layer is a conductive layer and includes an interconnect coupled to the first electrode;
- and
- a third layer on the second layer,
- wherein the interconnect is a first interconnect and the third layer is a conductive layer including a second interconnect which is coupled to the first interconnect, and
- wherein the second interconnect is an input node configured to receive the input signal.
An apparatus comprising:
- a layer including a region, the layer including:
- a first electrode on the region, including a gate of a first transistor and a gate of a second transistor;
- and
- a second electrode on the region, including a gate of a third transistor,
- wherein the gate of the first transistor and the gate of the second transistor are separated by the gate of the third transistor.
Dependencies are inferred from the claim text.