Input/output circuit and method

A circuit comprising:

• a plurality of power nodes configured to carry a corresponding plurality of voltage levels ranging from a first voltage level to a highest voltage level, wherein
• each voltage level of the plurality of voltage levels is a multiple of the first voltage level, a plurality of pairs of power nodes of the plurality of power nodes thereby corresponding to voltage levels differing by the first voltage level, and
• a highest power node of the plurality of power nodes corresponds to the highest voltage level of the plurality of voltage levels being a largest multiple greater than or equal to three;
• an input node configured to receive an input signal having a voltage swing from a reference voltage level to the first voltage level of the plurality of voltage levels;
• a first set of transistors coupled between an output node and the highest power node of the plurality of power nodes, a number of transistors in the first set of transistors being equal to the largest multiple;
• and
• a first control signal generation circuit comprising a first level shifting circuit, the first level shifting circuit comprising a first series of latch circuits coupled between each pair of power nodes of the plurality of pairs of power nodes,
• wherein the first control signal generation circuit is configured to, responsive to the input signal, output a first control signal to a gate of a first transistor of the first set of transistors closest to the highest power node of the plurality of power nodes.

A method of generating an output signal, the method comprising:

• receiving an input signal at an input node, the input signal switching between a reference voltage level and a first voltage level;
• using a plurality of latch circuits to upshift the input signal to a control signal switching between a second voltage level and a third voltage level equal to a sum of the first and second voltage levels;
• receiving the control signal at a gate of a first transistor of a set of transistors coupled between an output node and a first power node configured to carry the third voltage;
• and
• in response to the input signal and the control signal, using the set of transistors to generate the output signal on the output node,
• wherein
• the third voltage level is a multiple of the first voltage level, the multiple having a value greater than or equal to three,
• a number of transistors of the set of transistors is equal to the value of the multiple, and
• a number of latch circuits of the plurality of latch circuits is one less than the value of the multiple.