Data interface, chip, and chip system

A data interface comprising:

• a fourth metal-oxide-semiconductor (MOS) transistor, a voltage dividing circuit and a signal generating circuit;
• wherein a drain of the fourth MOS transistor is connected to one end of the voltage dividing circuit, the other end of the voltage dividing circuit is configured to receive a bias current, a gate of the fourth MOS transistor is configured to receive a bias voltage, and a source of the fourth MOS transistor is configured to receive a second voltage signal transmitted by a transmitting end;
• the two ends of the voltage dividing circuit are respectively connected to a first input end and a second input end of the signal generating circuit;
• and
• the signal generating circuit is configured to receive voltage signals at the two ends of the voltage dividing circuit and generate a fourth voltage signal according to the voltage signals at the two ends of the voltage dividing circuit.

A chip system comprising:

• a plurality of chips, wherein a first chip and a second chip of the plurality of chips are connected by using at least one data interface, wherein the data interface comprises:
• an electrostatic discharge circuit;
• and
• a charge transmitting circuit connected to a binding wire through the electrostatic discharge circuit, wherein the charge transmitting circuit comprises a first capacitor, the charge transmitting circuit transfers charges in the first capacitor to a parasitic capacitor of the electrostatic discharge circuit and a parasitic capacitor of the binding wire, to generate a first voltage signal and output the first voltage signal through the binding wire;
• and
• wherein the charge transmitting circuit further comprises:
• a first MOS transistor, a second MOS transistor and a third MOS transistor;
• wherein a source of the first MOS transistor is configured to receive a power supply voltage, a drain of the first MOS transistor is connected to the ground through the first capacitor, a gate of the first MOS transistor is configured to receive a first control signal, the drain of the first MOS transistor is connected to a source of the second MOS transistor, a drain of the second MOS transistor is configured to output the first voltage signal, a gate of the second MOS transistor is configured to receive the first control signal, and the drain of the second MOS transistor is connected to the ground through the third MOS transistor, and a gate of the third MOS transistor is configured to receive a second control signal.