IC layout tiles with internal channel for signal distribution

A method of manufacturing an integrated circuit, the method comprising:

• arranging multiple modular units to form an array, each modular unit in the array having an internal channel for signal distribution to adjacent modular units via edge connections on each edge of the modular unit, the internal channel including a hub node coupled to each edge connection by a respective bi-directional buffer having an incoming buffer and an outgoing buffer;
• coupling a source of a signal to one of the edge connections;
• and
• selectively disabling incoming and outgoing buffers of said bi-directional buffers to provide a signal distribution path from the source to each of the multiple modular units.

A method of distributing a clock signal, the method comprising:

• providing multiple modular units each having an internal channel that includes:
• an edge connection on each edge of the modular unit;
• a hub node coupled to each edge connection by a respective bi-directional buffer having an incoming buffer and an outgoing buffer;
• and
• a tap providing the clock signal for use by internal circuitry of the modular unit;
• electrically connecting each of the multiple modular units to one or more of the other multiple modular units via the edge connections to extend the internal channel across each of the multiple modular units;
• coupling a clock signal source to an edge connection of one of said multiple modular units;
• and
• disabling selected ones of the outgoing and incoming buffers to configure the internal channel as a clock distribution tree that conveys the clock signal to each of the multiple modular units.