Level shifter with deterministic output during power-up sequence

A level-shifting circuit, comprising:

• a plurality of p-type metal oxide semiconductor (PMOS) devices and n-type metal oxide semiconductor (NMOS) devices arranged and configured to level-shift an input voltage signal from a low voltage domain having a low voltage level to a high voltage domain having a high voltage level, to obtain an output voltage signal having an output voltage level at a first output node;
• a tie high circuit connected between the first output node and a high voltage terminal and including a tie high transistor configured to cause the first output node to be in a first pre-defined logic state during a power-up sequence of the level-shifting circuit in which the high voltage level becomes at least partially available prior to the low voltage level being reached;
• a tie low circuit that includes a tie low transistor connected between a ground terminal and a second output node that is complementary to the first output node, the tie low transistor configured to cause the second output node to be in a second pre-defined logic state during the power-up sequence;
• and
• a contention removal circuit connected to at least one of the plurality of PMOS and NMOS transistors in a leakage path that changes the first pre-defined logic state and thereby contends with the tie high circuit, the contention removal circuit powered by feedback from the second output node to equalize source terminal and drain terminal voltages across the at least one of the plurality of PMOS and NMOS transistors in the leakage path, to prevent the leakage current flowing therethrough.

A level-shifting circuit, comprising:

• a plurality of p-type metal oxide semiconductor (PMOS) devices and n-type metal oxide semiconductor (NMOS) devices arranged and configured to level-shift an input voltage signal from a low voltage domain having a low voltage level to a high voltage domain having a high voltage level during an operating region of the level-shifting circuit, the operating region occurring after a power up sequence of the low voltage domain and the high voltage domain in which the high voltage level becomes at least partially available prior to the low voltage level being reached;
• a tie high circuit connected between a high voltage terminal of the high voltage domain and a first output node of the level-shifting circuit, and biased by a first specified fraction of the high voltage level available during the power up sequence to conduct a first subthreshold current that ties the first output node to the high voltage level as the high voltage level increases during the power up sequence and until the low voltage level is reached;
• a tie low circuit connected between a second output node of the level-shifting circuit and ground, and biased by a second specified fraction of the high voltage level available during the power up sequence to conduct a second subthreshold current that ties the second output node to ground as the high voltage level increases during the power up sequence and until the low voltage level is reached;
• and
• a contention removal circuit connected to at least one of the plurality of PMOS and NMOS transistors in a leakage path that changes the second pre-defined logic state and thereby contends with the tie low circuit, the contention removal circuit powered by feedback from the first output node to equalize source terminal and drain terminal voltages across the at least one of the plurality of PMOS and NMOS transistors in the leakage path, to prevent the leakage current flowing therethrough.